Method and apparatus for clearing a region of Z-buffer
Granted: August 6, 1991
Patent Number:
5038297
A method and apparatus for clearing a Z-buffer in a raster scanned, computer controlled video display system having a frame buffer and a Z-buffer is disclosed. The method includes the step of writing a plurality of bits into pixel locations of the frame buffer, which pixel locations will be cleared in the Z-buffer and on the screen of the video display. Those plurality of bits invalidating the Z values in the Z-buffer corresponding to those pixel locations.
Graphics processor with staggered memory timing
Granted: February 5, 1991
Patent Number:
4991110
A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the…
Retaining means for removable computer drive and release means for same
Granted: October 2, 1990
Patent Number:
4960384
The present invention is a device for the easy installation and removal of a drive system from a computer housing. The invention also comprises a novel release button designed to activate the release mode of the drive system, and is also generally useful as a button assembly.
Method for updating pipelined, single port Z-buffer by segments on a scan line
Granted: August 21, 1990
Patent Number:
4951232
A method for updating a single ported, pipelined Z-buffer where the Z-buffer is updated only after determining the beginning and ending location of a continuous group of pixel locations requiring updating in the Z-buffer.
Interleaved pipeline parallel processing architecture
Granted: December 6, 1988
Patent Number:
4789927
A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor operating on only the first packet of data and the second processor operating on only the second packet of data.
Pixel mapping apparatus for color graphics display
Granted: September 20, 1988
Patent Number:
4772881
An improvement for providing color information in a raster scanned video display apparatus where color data is stored in a frame buffer for each pixel in addition to color data. The color data is coupled to a crossbar switch to provide several sets of color data at the output of the switch. A multiplexer receives these several sets of color information and selects between them based on the color mode data. This permits the same color code to represent more than a single color. In a…
Dual clock shift register
Granted: September 13, 1988
Patent Number:
4771279
YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.
