High memory capacity DRAM SIMM
Granted: December 21, 1993
Patent Number:
5272664
A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various…
Retaining and release mechanism for computer storage devices including a pawl latch assembly
Granted: December 14, 1993
Patent Number:
5269698
An assembly that couples a removable computer component to a computer is disclosed. The assembly has a disk drive or other similar device that is mounted onto a frame and is insertable into the opening of a computer housing. At one end of the opening is a first electrical connector mounted onto a rear wall of the housing. The disk drive is coupled to a second connector mounted onto the front end of the frame. The frame is inserted into the opening until the second connector mates with…
Apparatus and method for controlling storage of display information in a computer system
Granted: November 30, 1993
Patent Number:
5266941
A method and apparatus for controlling the storage of display information into a frame buffer is disclosed. A memory means is provided for storing information for controlling the storage of display information into the frame buffer where the memory means contains a plurality of locations each of which corresponds to and controls the storing of display information in one location of the frame buffer. A pass/fail ALU is coupled to the memory means to obtain a value for a particular pixel;…
Computer housing
Granted: November 23, 1993
Patent Number:
D341574
Method and apparatus for accomplishing Z-buffering by prediction
Granted: November 23, 1993
Patent Number:
5265199
A method for accelerating the writing of data to a Z buffer including the steps of reading the Z value presently stored at a position in the Z buffer; writing a new Z value to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote a new Z value to a position in the Z buffer, writing the Z value read back to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote the Z value read…
Variable page size per entry translation look-aside buffer
Granted: November 16, 1993
Patent Number:
5263140
A translation look-aside buffer with a variable page size per entry is disclosed. Each entry can have a different number of bits translated from a virtual address to a physical address. Each entry in the TLB contains an indication of the page size for that entry. When the translation is done, the indication of page size determines how many bits are translated.
Computer write-initiated special transferoperation
Granted: November 9, 1993
Patent Number:
5261074
A method for performing a transfer of digital information. A starting address is sent from a central processing unit of a digital computer to a bus, to a memory, and to a subsystem. A word count is sent from the central processing unit to a bus and to a subsystem. A block of data having a starting address that is the address of a first word in the block of data and having a word count that represents the number of words in the block of data is sent directly from the memory to the…
Translation lookaside buffer shutdown scheme
Granted: August 17, 1993
Patent Number:
5237671
Apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of…
Texture range controls for improved texture mapping
Granted: July 20, 1993
Patent Number:
5230039
A graphical display system and process for specifying and controlling a display range in which a specified form of texture mapping is applied or suppressed. Object data from a host computer is processed by four pipelined graphics subsystems before being displayed on a display screen. These graphics subsystems include: 1) a Geometry Subsystem, 2) a Scan Conversion Subsystem, 3) a Raster Subsystem, and 4) a Display Subsystem. Span Processors within the Scan Conversion Subsystem manipulate…
Electromagnetic shield for attachment to computers
Granted: July 13, 1993
Patent Number:
D337323
Two-level translation look-aside buffer using partial addresses for enhanced speed
Granted: July 6, 1993
Patent Number:
5226133
A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual…
File characterization for computer operating and file management systems
Granted: July 6, 1993
Patent Number:
5226163
A tool for characterization of files in a computer having an operating and file management system is described. The tool provides consistent definition and design of the functionality and appearance of icons and symbols used with operating environment programs.
Clock switching circuit for asynchronous clocks of graphics generation apparatus
Granted: March 23, 1993
Patent Number:
5197126
A circuit is described for providing switching between two asynchronous clocking signals in a graphics generation apparatus. In transitioning from one clocking signal to the other, the ending clocking signal ends at the end of a complete cycle, and the beginning clocking signal begins at the beginning of a new cycle. There is dead time between the clocking signals long enough to prevent transients which could disturb the operation of the system. The clocking signals are used to control…
Method and apparatus for producing a visually improved image in a computer system
Granted: March 9, 1993
Patent Number:
5193145
A method and apparatus for producing a visually improved image on a video display in a computer controlled display system. The system and method converts a quadrilateral polygon to a pair of triangles by computing the dot product of the normal unit vectors of one set of opposing pair of vectices and computing the dot product of the normal unit vectors of the other set of opposing pair of vertices and then comparing these two dot products to determine which opposing pair of vertices…
Bus control system for arbitrating requests with predetermined on/off time limitations
Granted: March 9, 1993
Patent Number:
5193193
A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory…
Method and apparatus for painting on a computer
Granted: January 26, 1993
Patent Number:
5182548
A method and apparatus for painting in a computer controlled video display system is described. A current shape of a brush stroke is determined. A current direction of the brush stroke is determined. A current position is determined. A current color is set equal to a color at the current position. The step of drawing the brush image on the display comprises the steps of setting a color of the brush image equal to the current color, setting a position of the brush image equal to the…
Synchronized DRAM control apparatus using two different clock rates
Granted: January 12, 1993
Patent Number:
5179667
A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory…
Graphics processor with staggered memory timing
Granted: July 7, 1992
Patent Number:
5129059
A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the…
Method for forming a computer model from an intersection of a cutting surface with a bounded volume
Granted: May 12, 1992
Patent Number:
5113490
A method for forming a computer model of a modified bounded volume representing a portion of a bounded volume on a cutting surface and to a first side of the cutting surface. After signed distances are calculated, either (1) the first face is modified by deleting the first edge from the first face of the bounded volume, (2) the first edge on the first face is retained, or (3) the first edge of the first face is modified by interpolation. The above steps are repeated for each of the…
Efficient graphics process for clipping polygons
Granted: September 24, 1991
Patent Number:
5051737
A system for displaying graphic images comprising an arrangement for clipping polygons against preselected clipping planes, an arrangement for determining when the vertices of a polygon all lie within one of a number of particular subspaces defined by the clipping planes, and an arrangement for disabling the means for clipping so long as all vertices of a polygon lie in the same subspace.
