Interlace motion artifact detection using vertical frequency detection and analysis
Granted: June 21, 2005
Patent Number:
6909469
An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the…
Method and apparatus for run length limited TMDS-like encoding of data
Granted: May 24, 2005
Patent Number:
6897793
A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments,…
Baud-rate timing recovery
Granted: May 10, 2005
Patent Number:
6891910
A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are extracted only from filter coefficients of feed-forward and feedback filters. The relation between the coefficients of feed-forward filter and the impulse response is derived under a zero-forcing condition while the relation between the coefficients of the feedback filter and the impulse response is…
Voltage controlled oscillator
Granted: May 3, 2005
Patent Number:
6888417
A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.
Wide range multi-phase delay-locked loop
Granted: April 5, 2005
Patent Number:
6876240
A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to…
Detection of video windows and graphics windows
Granted: March 29, 2005
Patent Number:
6873341
The invention relates to computer graphics and computer imaging on a video display, and includes the dynamic detection of video windows and graphical images overlapping one another. A display processor identifies differences between typical video and graphics data sources to detect the edges of video windows. By detecting the edges of active video windows within a graphics image, a display processor may uniquely adjust image characteristics of an exposed video window. These…
Methods and systems for TMDS encryption
Granted: March 22, 2005
Patent Number:
6870930
The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to…
Method, system and article of manufacture for identifying the source type and quality level of a video sequence
Granted: March 15, 2005
Patent Number:
6867814
A deinterlacing system which converts an interlaced video stream into a progressive video stream is disclosed. The deinterlacing system includes a field assembly responsive to a last field, a next field, a current field and progressive source phase and operative to develop a progressive output frame, a source detection module responsive to last, next and current fields and operative to develop a progressive source phase and a progressive source detected and an intra-frame deinterlacer…
Frequency comparator with hysteresis between locked and unlocked conditions
Granted: February 22, 2005
Patent Number:
6859107
A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference…
High-speed bus with embedded clock signals
Granted: January 18, 2005
Patent Number:
6845461
A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining…
Method and apparatus for connecting serial ATA storage components
Granted: January 18, 2005
Patent Number:
6843674
A method for connecting to an SATA storage component includes a chassis having an interior and an exterior, and a wall portion provided with an opening. An SATA compatible connector, provided with a first restraining flange and a second restraining flange spaced from the first restraining flange, is inserted into the opening in the wall portion, wherein an interior surface of the first restraining flange faces a first surface of the wall portion and an interior surface of the second…
Method and apparatus for detecting and smoothing diagonal features in video images
Granted: December 7, 2004
Patent Number:
6829013
A digital image processor includes an input buffer operable to receive an interlaced video stream and a digital memory for storing portions of the interlaced video stream. An output buffer is operable to transmit a deinterlaced video stream. Also included is a deinterlacing processor coupled between said input buffer and said output buffer and to said digital memory, said deinterlacing processor is operable to store portions of said received interlaced video stream from said input buffer…
Continuous-time, low-frequency-gain/high-frequency-boosting joint adaptation equalizer and method
Granted: November 16, 2004
Patent Number:
6819166
In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a…
Through-board PCB edge connector, system and method
Granted: November 9, 2004
Patent Number:
6814583
A female edge connector is cut into a circuit board to reduce the connector size and therefore the distance the signal path is separated from the ground plane. Preferably, the female connector is a surface mount connector and is provided in two pieces. This allows the female connector to be attached to either side of the printed circuit board or can be connected to both sides if half of the connector is mounted on the opposite side of the board from the other. A male edge connector of a…
System and method for multiple-phase clock generation
Granted: October 26, 2004
Patent Number:
6809567
A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified…
Method and system for DC-balancing at the physical layer
Granted: August 3, 2004
Patent Number:
6771192
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide…
Method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and method for determining such a block code
Granted: June 8, 2004
Patent Number:
6747580
A method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and a method for determining codebooks for use in such encoding or decoding. Some such methods select positive and negative codebooks that are complements of each other, including by eliminating all candidate code words having negative disparity and filtering the remaining candidate code words in automated fashion based on predetermined spectral properties to select a subset of the…
Method and apparatus for bidirectional data transfer between a digital display and a computer
Granted: May 18, 2004
Patent Number:
6738417
A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally…
Dynamically biased full-swing operation amplifier for an active matrix liquid crystal display driver
Granted: April 6, 2004
Patent Number:
6717468
A versatile amplifier circuit for driving a TFT LCD panel is disclosed. The amplifier circuit of the present comprises consists of a complementary input stage, biasing switches, and a rail-to-rail output stage. A signal-transfer switch determines which of two differential amplifiers in the input stage will drive the output stage of the amplifier. A biasing signal precharges a capacitor between the gates of output stage. The rail-to-rail output stage utilizes the precharged capacitor to…
Multi-phase voltage controlled oscillator (VCO) with common mode control
Granted: April 6, 2004
Patent Number:
6717478
A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the…
