Method and system for spatial-temporal dithering for displays with overlapping pixels
Granted: March 30, 2004
Patent Number:
6714206
A method and system for establishing intensity levels for sub-pixels of a display device with overlapping logical pixels. The dithering system combines frame rate control techniques with contributions from overlapping pixels to establish the intensity level of each sub-pixel. The dithering system initially provides an assignment of frame numbers to each sub-pixel. The dithering system then receives a logical pixel color that includes an intensity value for each component color (e.g.,…
Clock and data recovery method and apparatus
Granted: February 17, 2004
Patent Number:
6693985
Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal.…
Method of testing serial interface
Granted: September 23, 2003
Patent Number:
6625560
A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase…
Spread spectrum phase modulation for suppression of electromagnetic interference in parallel data channels
Granted: July 29, 2003
Patent Number:
6600771
A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.
System and method for high-speed, synchronized data communication
Granted: July 1, 2003
Patent Number:
6587525
A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within…
Bi-directional data transfer using the video blanking period in a digital data stream
Granted: May 13, 2003
Patent Number:
6564269
Digital pixel data is transferred from a computer system to video display hardware in a forward direction. However, there are many reasons for digital pixel data to be transferred in both directions along a cable connecting a computer and a monitor. This invention describes a method of sending digital data from a monitor back to the computer in a reverse direction. In transmission of digital pixel data in a forward direction, there are horizontal and vertical blanking periods during…
CMOS driver and on-chip termination for gigabaud speed data communication
Granted: May 6, 2003
Patent Number:
6560290
New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a…
Fully differential continuous-time current-mode high speed CMOS comparator
Granted: March 18, 2003
Patent Number:
6535029
A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias…
High-speed and high-precision phase locked loop
Granted: October 8, 2002
Patent Number:
6462624
A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase…
System and method for sending and receiving data signals over a clock signal line
Granted: October 8, 2002
Patent Number:
6463092
The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver…
Methods and apparatus for variable length SDRAM transfers
Granted: May 7, 2002
Patent Number:
6385692
Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in…
Skew-insensitive low voltage differential receiver
Granted: April 16, 2002
Patent Number:
6374361
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the converted full-swing clock signal, and a plurality of data recovery signals from the converted full-swing…
Wide frequency-range delay-locked loop circuit
Granted: December 4, 2001
Patent Number:
6326826
A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges.…
Bi-directional data transfer using two pair of differential lines as a single additional differential pair
Granted: October 23, 2001
Patent Number:
6307543
Data is transferred from a processor to a display in one direction. However, there are many reasons for data to be transferred in both directions along a cable connecting the processor and display. This invention describes a method of sending data from the display back to the processor computer in a situation in which the video data transferred to the display is in digital form. Differential wire pairs are used to transmit red, green and blue digital pixel data in a first direction from…
Power saving circuit and method for driving an active matrix display
Granted: August 7, 2001
Patent Number:
6271816
Switches and capacitors are efficiently used to passively change the voltage level on column electrodes without active driving by the column driver circuit. This significantly reduces the power needed by the column driver circuit to drive voltages of alternating polarity onto the column electrodes. In this way, significant power is saved in both the pixel inversion and the row inversion schemes. The average power savings of various of the embodiments exceeds 50% compared with a simple…
Scaling multi-dimensional signals using variable weighting factors
Granted: July 10, 2001
Patent Number:
6259427
An image or other multi-dimensional data set may have its sampling rate changed by determining weighting factors for the values of points in the original (input) data set used to calculate the value of a point in the new (output) data set. The weighting factors are determined using a function, such as a Gaussian function, that takes as input the relative location of the point in the new data set with respect to the locations of surrounding (neighboring) points in the original data set.…
System and method for high-speed, synchronized data communication
Granted: May 8, 2001
Patent Number:
6229859
A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within…
High-speed and high-precision phase locked loop having phase detector with dynamic logic structure
Granted: December 5, 2000
Patent Number:
6157263
A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase…
System and method for driving columns of an active matrix display
Granted: December 5, 2000
Patent Number:
6157360
Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps--the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns…
System and method for sending multiple data signals over a serial link
Granted: November 21, 2000
Patent Number:
6151334
A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate…
