Bi-directional bridge circuit having high common mode rejection and high input sensitivity
Granted: February 14, 2012
Patent Number:
8116240
A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate…
Error detection in physical interfaces for point-to-point communications between integrated circuits
Granted: January 17, 2012
Patent Number:
8099648
An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input…
Method, apparatus and system for generating and facilitating mobile high-definition multimedia interface
Granted: January 3, 2012
Patent Number:
8090030
A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled…
Noise cancellation
Granted: December 27, 2011
Patent Number:
8086067
A technique for reducing noise in a digital video signal is disclosed. In one embodiment, the technique involves receiving a digital signal. The digital signal can be filtered thereby generating a filtered signal. The digital signal and the filtered signal can be mixed according to a composite blend map thereby generating an optimized signal. The optimized signal can be provided as an output.
Group power management of network devices
Granted: December 27, 2011
Patent Number:
8086886
A method and apparatus for group power management of network devices. Some embodiments of an apparatus include a power management module, where the power management module is to transition the apparatus from a normal state to a low power state. The apparatus includes a wake module having a processor that remains active in the low power state, and a register to store a group address. The apparatus includes a network interface that is monitored by the processor in the low power state,…
Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer
Granted: November 22, 2011
Patent Number:
8064508
An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative…
Method, apparatus, and system for automatic data aligner for multiple serial receivers
Granted: October 11, 2011
Patent Number:
8036248
A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay…
Fault testing for interconnections
Granted: September 27, 2011
Patent Number:
8026726
Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes…
Original scan line detection
Granted: August 23, 2011
Patent Number:
8004606
A technique for detecting original scan lines is disclosed. The technique involves receiving a deinterlaced signal with even scan lines and odd scan lines. After the deinterlaced signal is received, a determination is made as to whether the even scan lines or the odd scan lines are the original scan lines. In certain embodiments, an interlaced signal can be generated from the original scan lines. In other embodiments, an optimized deinterlaced signal can be generated using the original…
Bank sharing and refresh in a shared multi-port memory device
Granted: August 16, 2011
Patent Number:
8001334
A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the…
Data sampling method and apparatus using through-transition counts to reject worst sampling position
Granted: August 2, 2011
Patent Number:
7991096
A data sampling circuit that employs an oversampling clock to oversample a data signal, a phase tracking circuit for use in such a sampling circuit, and a receiver and system including such a sampling circuit. Preferably, phase tracking is implemented by systematically identifying and rejecting at least one worst sampling position, and sampling the data signal at a non-rejected sampling position. Preferably, phase tracking is accomplished by counting through-transitions of edges of the…
Edge detection
Granted: July 19, 2011
Patent Number:
7982798
A technique for deinterlacing an interlaced video stream is disclosed. A method according to the technique can involve calculating a gradient of image intensity and identifying an edge. A bin can be selected that encompasses the edge. An unknown pixel can be calculated by blending known pixel values along the bin boundaries.
Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features
Granted: July 19, 2011
Patent Number:
7984369
Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a…
17B/20B coding system
Granted: July 12, 2011
Patent Number:
7978099
A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of…
Method, apparatus, and system for port multiplier enhancement
Granted: July 12, 2011
Patent Number:
7979589
A method, apparatus and system are provided for enhancing port multipliers. In one embodiment, a port multiplier is configured to couple a network host with port multipliers. The port multiplier includes a top port multiplier to establish and maintain communication with each of the port multipliers to communicate with the network host, and the port multipliers having intermediate port multipliers and/or bottom port multipliers. Further, network devices are in communication with the port…
Inter-port communication in a multi-port memory device
Granted: May 24, 2011
Patent Number:
7949863
A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer…
Synchronizing related data streams in interconnection networks
Granted: May 3, 2011
Patent Number:
7936790
A method and apparatus for synchronizing related data streams in interconnection networks. Some embodiments of an apparatus include a transmitter to transmit a data stream to a second apparatus, where the transmitter transmits a data packet to the second apparatus. The apparatus further includes a clock, with the apparatus providing a first timestamp for the data packet using the clock upon transmission of the data packet. The apparatus includes a receiver to receive responses from the…
Error detection in physical interfaces for point-to-point communications between integrated circuits
Granted: May 3, 2011
Patent Number:
7937644
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical…
Discovery of electronic devices utilizing a control bus
Granted: April 5, 2011
Patent Number:
7921231
Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a…
Packet level prioritization in interconnection networks
Granted: March 22, 2011
Patent Number:
7911956
A method and apparatus for packet level prioritization in interconnection networks. An embodiment of an apparatus includes a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets, the data packets including data packets of a first priority and data packets of a second priority. The apparatus further includes a network unit to direct the operation of the transmitter, the network unit to divide the data stream into multiple…
