Progressive power control of a multi-port memory device
Granted: March 15, 2011
Patent Number:
7908501
A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and…
Bandwidth reservation for data flows in interconnection networks
Granted: March 8, 2011
Patent Number:
7903550
A method and apparatus for bandwidth reservation for data flows in interconnection networks. Some embodiments of an apparatus for transmitting a data stream include a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets. The apparatus further includes a receiver to receive a response from the recipient apparatus regarding data packet arrival status, and a network unit to direct the operation of the transmitter, the network…
Communications architecture for transmission of data between memory bank caches and ports
Granted: March 8, 2011
Patent Number:
7903684
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide…
Method, apparatus, and system for employing an enhanced port multiplier
Granted: March 8, 2011
Patent Number:
7904566
A method, apparatus and system for employing an enhanced port multiplier are provided. In one embodiment, a network host is configured to be coupled with a port multiplier in a network. The port multiplier is configured into being cascaded into being coupled with a plurality of port multipliers and a plurality of network devices.
Method and apparatus for encrypting data transmitted over a serial link
Granted: March 1, 2011
Patent Number:
7900047
A communication system including a transmitter, a receiver, and a serial link (for example, a TMDS-like link) in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are decrypted in the receiver, a transmitter and a receiver for use in such systems, a cipher engine for use in such a transmitter or receiver, a method for operating such a transmitter or receiver to encrypt or decrypt data, and a…
Current mode circuitry to modulate a common mode voltage
Granted: January 18, 2011
Patent Number:
7872498
In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received…
Control bus for connection of electronic devices
Granted: December 21, 2010
Patent Number:
7856520
A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming…
Transmitter and receiver using asymmetric transfer characteristics in differential amplifiers to suppress noise
Granted: December 7, 2010
Patent Number:
7847583
An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended…
Power-saving clocking technique
Granted: December 7, 2010
Patent Number:
7849339
A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the…
Parallel interface bus to communicate video data encoded for serial data links
Granted: November 30, 2010
Patent Number:
7844762
In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used to represent a pixel such that pixels are represented in more than one of the parallel groups. The parallel sink is to receive the parallel groups of signals from the bus, wherein the parallel sink includes a signal extractor…
Scan-based testing of devices implementing a test clock control structure (“TCCS”)
Granted: November 23, 2010
Patent Number:
7840861
Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. It also includes performing an inter-domain test to exercise a second subset of domains of the plurality of circuits implementing dynamic fault detection test…
Operation of media interface to provide bidirectional communications
Granted: November 16, 2010
Patent Number:
7836223
Embodiments of the invention are generally directed to operation of a media interface to provide bidirectional communications. An embodiment of a method includes connecting a first device to a second device via a media interface, the media interface including a communication channels for unidirectional data transmission, the media interface being in compliance with a media protocol. The method further provides for configuring the first device and the second device for bidirectional data…
Shared nonvolatile memory architecture
Granted: November 9, 2010
Patent Number:
7831778
A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find…
Circuitry to prevent peak power problems during scan shift
Granted: November 9, 2010
Patent Number:
7831877
In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry…
Cryptographic device with stored key data and method for using stored key data to perform an authentication exchange or self test
Granted: September 14, 2010
Patent Number:
7797536
In preferred embodiments, a cryptographic device in which two key sets are stored: a normal key set (typically unique to the device) and a test key set (typically used by each of a relatively large number of devices). The device uses the normal key set in a normal operating mode and uses the test key set in at least one test mode which can be a built-in self test mode. Alternatively, the device stores test data (e.g., an intermediate result of an authentication exchange) in addition to…
Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers
Granted: September 7, 2010
Patent Number:
7793179
Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure includes a programmable test clock controller. The programmable test clock controller includes a test clock generator for generating a configurable test clock. It also includes a scan layer interface to drive a scan chain portion with the configurable test clock, and a control layer interface…
Parameter scanning for signal over-sampling
Granted: August 24, 2010
Patent Number:
7782934
A method and apparatus for parameter scanning for signal over-sampling. An embodiment of an apparatus includes an equalizer to equalize received data values, and a sampler to over-sample the equalized data. The apparatus includes an eye monitor to generate information regarding quality of signal eyes for the over-sampled data, and an equalization monitor to generate information regarding sufficiency of signal equalization. The apparatus further includes a scan engine to scan possible…
Coding system for memory systems employing high-speed serial links
Granted: August 17, 2010
Patent Number:
7777652
A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second…
Method and apparatus for encrypting data transmitted over a serial link
Granted: July 13, 2010
Patent Number:
7757085
A system for implementing a content protection protocol to encrypt data, including transmitters and receivers to which key selection vectors of a vector set have been distributed, wherein a subset of the key selection vectors in the vector set has not been distributed to any of the transmitters or any of the receivers, and a method for enabling transmitters and receivers to implement a content protection protocol including by distributing key selection vectors of a vector set, and…
Method and system for integrating packet type information with synchronization symbols
Granted: June 29, 2010
Patent Number:
7746798
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide…
