Method and apparatus for content protection in a personal digital network environment
Granted: April 20, 2010
Patent Number:
7702925
In some embodiments, the invention is a personal digital network (“PDN”) including hardware (sometimes referred to as Ingress circuitry) configured to transcrypt encrypted content that enters the PDN. Typically, the transcryption (decryption followed by re-encryption) is performed in hardware within the Ingress circuitry and the re-encryption occurs before the decrypted content is accessible by hardware or software external to the Ingress circuitry. Typically, transcrypted content…
Interface test circuitry and methods
Granted: April 13, 2010
Patent Number:
7698088
In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match…
Error detection in physical interfaces for point-to-point communications between integrated circuits
Granted: April 6, 2010
Patent Number:
7694204
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor…
Multi-port memory device having variable port speeds
Granted: December 29, 2009
Patent Number:
7639561
A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider…
Interlace motion artifact detection using vertical frequency detection and analysis
Granted: December 15, 2009
Patent Number:
7633559
An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the…
Clock-edge modulated serial link with DC-balance control
Granted: December 1, 2009
Patent Number:
7627044
A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
Adaptive bandwidth phase locked loop with feedforward divider
Granted: October 13, 2009
Patent Number:
7602253
In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other…
Bi-directional bridge circuit having high common mode rejection and high input sensitivity
Granted: October 6, 2009
Patent Number:
7599316
A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate…
Method and system for transmitting N-bit video data over a serial link
Granted: October 6, 2009
Patent Number:
7599439
A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the…
Current mode circuitry to modulate a common mode voltage
Granted: September 15, 2009
Patent Number:
7589559
In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received…
Covert channel for conveying supplemental messages in a protocol-defined link for a system of storage devices
Granted: August 4, 2009
Patent Number:
7571269
Disclosed are communication apparatus, a SATA communication device, a system, an enhanced port multiplier and a method for, among other things, establishing a covert communication channel in a protocol-compliant link. In one embodiment, a communication apparatus includes a link interface and a supplemental message interface. The link interface is configured to communicatively couple the communication apparatus to the link for accessing a data stream passing through the link in accordance…
Digital display jitter correction apparatus and method
Granted: July 7, 2009
Patent Number:
7557863
A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the…
Method and apparatus for sending auxiliary data on a TMDS-like link
Granted: July 7, 2009
Patent Number:
7558326
A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver, and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the receiver to the transmitter. In typical…
Auxiliary data transmitted within a display's serialized data stream
Granted: June 30, 2009
Patent Number:
7555693
Techniques to transmit auxiliary data are disclosed. One technique includes generating a control signal from a video data enable signal and an auxiliary data enable signal, and combining an auxiliary data signal and a video data signal into a composite data signal using the control signal. Techniques to receive the auxiliary data are also disclosed.
CMOS transceiver with dual current path VCO
Granted: June 23, 2009
Patent Number:
7551909
A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock…
Integrated circuit having self test capability using message digest and method for testing integrated circuit having message digest generation circuitry
Granted: May 26, 2009
Patent Number:
7539304
An integrated circuit that includes operational circuitry and message digest generation circuitry coupled to the operational circuitry, a method for testing an integrated circuit including message digest generation circuitry, and a system including an integrated circuit (which includes message digest generation circuitry) and at least one external device coupled to the integrated circuit. The message digest generation circuitry is coupled and configured to generate at least one digest of…
Method for switching data in a crossbar switch
Granted: April 14, 2009
Patent Number:
7519066
A method and system for switching data in a data switch. In one embodiment, the present invention comprises receiving a plurality of cells at a merged input queue of the data switch, wherein a cell of the plurality of cells is characterized by a priority and a destination. In one embodiment, the destination identifies an output port of the data switch. An age tag is assigned to at least one cell of the plurality of cells. In one embodiment, the age tag indicates the relative length of…
Method and apparatus for data recovery in a digital data stream using data eye tracking
Granted: April 14, 2009
Patent Number:
7519138
A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare…
Preference programmable first-one detector and quadrature based random grant generator
Granted: March 17, 2009
Patent Number:
7505422
A preference programmable first-one detector and quadrature based random grant generator in a crossbar switch is disclosed. The crossbar switch emulates a FIFO switching function in a single chip crossbar switch architecture that operates at a high switching speed with a large bandwidth and supports multiple QoS levels, yet do not demand an inordinately large number of input and output queues or otherwise excessively tax memory requirements. The system and method operate at a high…
Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals
Granted: March 10, 2009
Patent Number:
7502411
In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized…
