MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION
Granted: December 13, 2012
Application Number:
20120317348
A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory…
Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device
Granted: November 29, 2012
Application Number:
20120302017
A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching…
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
Granted: November 22, 2012
Application Number:
20120294103
A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and…
APPARATUS AND METHOD FOR EXTERNAL CHARGE PUMP ON FLASH MEMORY MODULE
Granted: November 1, 2012
Application Number:
20120275229
A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.
METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY WRITE ALGORITHM FOR FAST BITS
Granted: November 1, 2012
Application Number:
20120275231
A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the…
METHOD AND APPARATUS FOR TEMPERATURE COMPENSATION FOR PROGRAMMING AND ERASE DISTRIBUTIONS IN A FLASH MEMORY
Granted: November 1, 2012
Application Number:
20120275235
A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is…
RELOCATING DATA IN A MEMORY DEVICE
Granted: October 25, 2012
Application Number:
20120271991
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources.…
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE
Granted: September 27, 2012
Application Number:
20120241871
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies…
ELECTRONIC DEVICES WITH ULTRAVIOLET BLOCKING LAYERS AND PROCESSES OF FORMING THE SAME
Granted: August 30, 2012
Application Number:
20120218700
An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the…
PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD
Granted: August 9, 2012
Application Number:
20120202355
A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a…
NON-VOLATILE FINFET MEMORY ARRAY AND MANUFACTURING METHOD THEREOF
Granted: July 19, 2012
Application Number:
20120181591
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the…
SYSTEM, METHOD AND APPARATUS FOR REDUCING PLASMA NOISE ON POWER PATH OF ELECTROSTATIC CHUCK
Granted: June 28, 2012
Application Number:
20120160807
A vacuum plasma system has a table with a table power connector, and a fixture spaced apart from the table for defining a chamber between the table and the fixture. An electrostatic chuck (ESC) is mounted to the table in the chamber. The ESC has a side for supporting a workpiece, and an ESC power connector that electrically couples with the table power connector. A coupling extends between the table and ESC power connectors to provide electrical connection therebetween. A shield…
METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION
Granted: June 7, 2012
Application Number:
20120139023
A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line.
DUAL SPACER FORMATION IN FLASH MEMORY
Granted: June 7, 2012
Application Number:
20120142175
A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills…
RETENTION IN NVM WITH TOP OR BOTTOM INJECTION
Granted: May 24, 2012
Application Number:
20120127796
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell…
APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE
Granted: March 15, 2012
Application Number:
20120063243
A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal…
Apparatus and method for read preamble disable
Granted: March 15, 2012
Application Number:
20120066433
A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response…
APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE
Granted: March 15, 2012
Application Number:
20120066434
A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.
APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE
Granted: March 15, 2012
Application Number:
20120066464
A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides…
METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
Granted: March 8, 2012
Application Number:
20120056260
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral…
