RESISTANCE CHANGING MEMORY CELL ARCHITECTURE
Granted: March 1, 2012
Application Number:
20120051115
A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a…
BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME
Granted: February 16, 2012
Application Number:
20120038051
A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom…
METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION
Granted: February 9, 2012
Application Number:
20120034755
A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching and gap fill, the nitride above the high voltage gate oxide regions are etched, and the oxide in high voltage gate oxide regions is grown to the appropriate thickness for a high voltage gate oxide.
GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS
Granted: February 9, 2012
Application Number:
20120032308
Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and…
HIGH READ SPEED MEMORY WITH GATE ISOLATION
Granted: December 29, 2011
Application Number:
20110317466
Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase…
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB
Granted: November 17, 2011
Application Number:
20110278660
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the…
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
Granted: September 29, 2011
Application Number:
20110238866
One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then…
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
Granted: September 29, 2011
Application Number:
20110237060
Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a…
FUEL CELL CATALYST REGENERATION
Granted: September 29, 2011
Application Number:
20110236773
Systems that facilitate operating proton exchange membrane (PEM) fuel cells are provided. The systems employ a fuel supply component that supplies fuel to the proton exchange membrane fuel cell; and a regeneration component that provides a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma to a cathode catalyst of the proton exchange membrane fuel cell to reduce the cathode catalyst.
MEMORY DEVICE AND METHOD
Granted: September 29, 2011
Application Number:
20110235430
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a…
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
Granted: September 29, 2011
Application Number:
20110235412
A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and…
NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Granted: September 15, 2011
Application Number:
20110220981
Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type…
NAND ARRAY SOURCE/DRAIN DOPING SCHEME
Granted: September 15, 2011
Application Number:
20110221006
An electronic device includes a substrate having isolation features defining active regions coextending over a surface of the substrate. The device also includes coextending line patterns crossing over the active regions, including string and ground selection lines and word lines between the string and ground selection lines. The device further includes first implant regions of a first conductivity type in the active regions between the word lines and having a first carrier…
HOME AND BUILDING AUTOMATION
Granted: September 15, 2011
Application Number:
20110224810
Systems (100) and methods (500) for controlling a household electronic device (HED). The HED (102, . . . , 114, 142) comprises a processing unit (302) configured to execute first device-control software operative for controlling the HED so that it performs a primary function using original values for a plurality of operating parameters. The methods involve receiving, at the HED, an active processing module (130, . . . , 140, 144, 146) configured to execute second device-control software.…
SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE
Granted: September 15, 2011
Application Number:
20110225327
Systems and methods (600) for controlling an electronic device (100) with an active processing module (308) having a first and second input/output interface (502, 504). The methods involve interfacing the active processing module and a computing device using the first input/output interface of the active processing module. Thereafter, the active processing module is programmed using a user interface of the computing device. The method also involves interfacing the active processing…
ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
Granted: September 15, 2011
Application Number:
20110225348
System and methods for assembling electronic devices (110) using removable programmable active processing modules (120) are provided. An active processing module includes a first input/output (I/O) interface (202) and a second I/O interface (204). The active processing module also includes a controller (206) communicatively coupled to the first and the second I/O interfaces, where the controller is configured for selectively operating the active processing module in a programming mode or…
APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY
Granted: August 18, 2011
Application Number:
20110199819
A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the…
PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH
Granted: August 11, 2011
Application Number:
20110195578
A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is…
JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
Granted: July 21, 2011
Application Number:
20110176363
A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate…
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
Granted: July 21, 2011
Application Number:
20110179319
An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is…
