MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE
Granted: July 9, 2015
Application Number:
20150194537
A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second…
Formation of Gate Sidewall Structure
Granted: July 2, 2015
Application Number:
20150187891
A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall…
Gate Formation Memory by Planarization
Granted: June 25, 2015
Application Number:
20150179817
Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion…
CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE
Granted: June 25, 2015
Application Number:
20150179656
Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to…
PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES
Granted: June 18, 2015
Application Number:
20150171100
A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is…
INCREASING LITHOGRAPHIC DEPTH OF FOCUS WINDOW USING WAFER TOPOGRAPHY
Granted: June 18, 2015
Application Number:
20150168851
Various embodiments provide for topography aware optical proximity correction that can improve depth of focus during wafer lithography. The system can determine the topography of the wafer using real process information. The topographical variations can be based on random defects or structural details. The system can divide the wafer into regions based on the topography of the regions and determine depth of focus values for each of the regions. Optical proximity correction can then be…
Forming Charge Trap Separation in a Flash Memory Semiconductor Device
Granted: June 11, 2015
Application Number:
20150162226
During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor,…
SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD
Granted: June 11, 2015
Application Number:
20150161320
A computer-implemented method is disclosed for optimizing one or more sub-resolution assist features for use in a photolithographic process. The method may include incorporating a sub-resolution assist feature within a virtual photomask. The virtual photomask may then be modeled to produce a virtual print. One or more intensity values corresponding to the sub-resolution assist feature may be collected from the virtual print. Based on the one or more intensity values, a probability of…
GENERATION OF WAKE-UP WORDS
Granted: June 4, 2015
Application Number:
20150154953
A method, system and tangible computer readable medium for generating one or more wake-up words are provided. For example, the method can include receiving a text representation of the one or more wake-up words. A strength of the text representation of the one or more wake-up words can be determined based on one or more static measures. The method can also include receiving an audio representation of the one or more wake-up words. A strength of the audio representation of the one or more…
Reduction of Charging Induced Damage in Photolithography Wet Process
Granted: June 4, 2015
Application Number:
20150155162
An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse.
Auto Resume of Irregular Erase Stoppage of a Memory Sector
Granted: May 28, 2015
Application Number:
20150149696
Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the…
Output Switching Circuit
Granted: May 14, 2015
Application Number:
20150130430
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating…
METHODS, CIRCUITS, SYSTEMS AND COMPUTER EXECUTABLE INSTRUCTION SETS FOR PROVIDING ERROR CORRECTION OF STORED DATA AND DATA STORAGE DEVICES UTILIZING SAME
Granted: May 7, 2015
Application Number:
20150128011
Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.
DEVICE FOR EMITTING LIGHT BY MEANS OF LEDS OF THE CONTINUOUS AND PULSED TYPE FOR AESTHETIC AND THERAPEUTIC TREATMENTS
Granted: May 7, 2015
Application Number:
20150127072
A device for emitting light by means of LEDs of the continuous and pulsed type for aesthetic and therapeutic treatments, of the type comprising an electric power supply circuit which is connected to a respective external control and management unit and at least one LED controlled by the circuit and oriented toward a surface that is intended to face the skin of the patient in conditions for use, the device having a platelike shape; the at least one LED being arranged on a laminar…
Multiple Phase-Shift Photomask and Semiconductor Manufacturing Method
Granted: April 23, 2015
Application Number:
20150109594
Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device…
Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film
Granted: April 23, 2015
Application Number:
20150108562
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel…
ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SHAPE AND SPACER WIDTH CONTROL
Granted: April 16, 2015
Application Number:
20150102400
Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a…
MEMORY PROGRAM UPON SYSTEM FAILURE
Granted: April 16, 2015
Application Number:
20150106662
A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer…
MULTI-PASS SOFT PROGRAMMING
Granted: April 16, 2015
Application Number:
20150103601
Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a…
Spacer Formation with Straight Sidewall
Granted: April 16, 2015
Application Number:
20150102430
Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and…
