METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE
Granted: April 16, 2015
Application Number:
20150106664
Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture.…
HIDDEN MARKOV MODEL PROCESSING ENGINE
Granted: April 16, 2015
Application Number:
20150106405
A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one…
METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR PROVIDING CURRENT TO A NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY
Granted: April 9, 2015
Application Number:
20150098290
Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating…
SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
Granted: April 9, 2015
Application Number:
20150097245
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench…
BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS
Granted: April 9, 2015
Application Number:
20150097224
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench…
Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
Granted: April 2, 2015
Application Number:
20150091138
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
CHIP POSITIONING IN MULTI-CHIP PACKAGE
Granted: February 26, 2015
Application Number:
20150056726
Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An…
APPARATUS AND METHOD FOR SMART VCC TRIP POINT DESIGN FOR TESTABILITY
Granted: February 26, 2015
Application Number:
20150054554
An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output…
SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING THE SAME, AND METHOD OF MANUFACTURING THE SAME
Granted: January 1, 2015
Application Number:
20150001611
The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact…
Non-Volatile Finfet Memory Array and Manufacturing Method Thereof
Granted: December 18, 2014
Application Number:
20140370698
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device. the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the…
Differential File System for Computer Memory
Granted: November 27, 2014
Application Number:
20140351485
An approach is described to overcome the rapid consumption of available flash space when frequently modifying files stored on the flash space. This “differential” sector approach determines the correlation between the new content and the old content, and saves only the “delta” part of the old and the new content to the sectorized memory device. A predetermined threshold can be used to determine whether to use the “differential” sector approach or the fixed sector approach,…
COMBINING OF RESULTS FROM MULTIPLE DECODERS
Granted: October 9, 2014
Application Number:
20140304205
Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number…
AUTHENTICATION FOR RECOGNITION SYSTEMS
Granted: October 9, 2014
Application Number:
20140303983
Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.
MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS
Granted: October 9, 2014
Application Number:
20140301146
A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias…
Inter-Bus Communication Interface Device
Granted: September 25, 2014
Application Number:
20140289443
There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the…
Node System and Supervisory Node
Granted: September 25, 2014
Application Number:
20140286330
A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
SEMICONDUCTOR DEVICE HAVING CHIP MOUNTED ON AN INTERPOSER
Granted: September 11, 2014
Application Number:
20140256088
A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package 10; a second semiconductor package 20 mounted on an upper surface of the first molding resin 14; a second interposer 22 on which the second semiconductor package 20 is mounted by flip…
Pipelining in a Memory
Granted: September 11, 2014
Application Number:
20140254288
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION
Granted: August 28, 2014
Application Number:
20140244914
A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory…
APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
Granted: August 21, 2014
Application Number:
20140233339
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
