AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
Granted: July 12, 2007
Application Number:
20070159198
The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms…
Method for fabricating a semiconductor device
Granted: June 7, 2007
Application Number:
20070128885
A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step of further depositing the insulation film 32b with the second pressure set in the deposition chamber. The insulation film is deposited with the first pressure a little lower than a second…
Semiconductor memory device
Granted: May 24, 2007
Application Number:
20070114617
A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped…
Semiconductor memory device (as amended)
Granted: May 24, 2007
Application Number:
20070117303
A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped…
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
Granted: May 10, 2007
Application Number:
20070102743
Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive…
System and method for processing an organic memory cell
Granted: April 26, 2007
Application Number:
20070090343
A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The…
Semiconductor memory device comprising one or more injecting bilayer electrodes
Granted: March 15, 2007
Application Number:
20070058426
The subject invention provides systems and methods that facilitate formation of semiconductor memory devices comprising memory cells with one or more injecting bilayer electrodes. Memory arrays generally comprise bit cells that have two discrete components; a memory element and a selection element, such as, for example, a diode. The invention increases the efficiency of a memory device by forming memory cells with selection diodes comprising a bilayer electrode. Memory cells are provided…
Program/erase waveshaping control to increase data retention of a memory cell
Granted: February 1, 2007
Application Number:
20070025166
System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final…
Vertical JFET as used for selective component in a memory array
Granted: March 9, 2006
Application Number:
20060049435
Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell in a memory array while increasing device density in the memory cell array. A vertical JFET is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell coupled to the vertical JFET. By mitigating gaps between gates, or wordlines, and drains of the vertical…
Polymer memory device with variable period of retention time
Granted: February 23, 2006
Application Number:
20060038169
Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming the polymer memory cell via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to…
Systems and methods for adjusting programming thresholds of polymer memory cells
Granted: February 23, 2006
Application Number:
20060038982
Systems and methodologies are provided for adjusting threshold associated with a polymer memory cell's operation by applying thereupon a regulated electric field and/or voltage pulse width, during a post fabrication stage. Such customization of programming thresholds can typically be obtained at any cycle of programming the memory cell, to increase flexibility in circuit design. Accordingly, the present invention supplies both a current-voltage domain, and/or a frequency-time domain, to…
Semiconductor memory device and manufacturing method thereof
Granted: October 20, 2005
Application Number:
20050230714
A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped…
