SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
Granted: May 8, 2008
Application Number:
20080109903
An architecture is presented that facilitates integrated security capabilities. A memory module is provided that comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. Further, a host processor located outside of the memory module arbitrates with the security processor for access to the non-volatile memory. The memory module…
CONTACTS FOR SEMICONDUCTOR DEVICES
Granted: April 24, 2008
Application Number:
20080096348
A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.
PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
Granted: April 24, 2008
Application Number:
20080096388
A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component,…
Virtual memory card controller
Granted: April 17, 2008
Application Number:
20080091878
The claimed subject matter can provide an architecture that can transparently provide more robust interactions between a host device and a smartcard or other mass media storage device by way of block level read or write operations provided as part of a standard interface protocol. A virtual controller can be installed on the smartcard to manage access to the data store of a smartcard. The virtual controller can provide special objects (e.g., files, directories, partitions . . . ) to the…
MEMORY CELL SYSTEM WITH CHARGE TRAP
Granted: April 10, 2008
Application Number:
20080083946
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
Exhaust system
Granted: March 27, 2008
Application Number:
20080072585
An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with…
MEMORY ERASE MANAGEMENT SYSTEM
Granted: March 13, 2008
Application Number:
20080062739
A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
MULTIPLE COMMUNICATION CHANNELS ON MMC OR SD CMD LINE
Granted: March 6, 2008
Application Number:
20080059668
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g. a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be…
FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
Granted: February 28, 2008
Application Number:
20080049516
A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is…
MEMORY CELL SYSTEM WITH GRADIENT CHARGE ISOLATION
Granted: February 7, 2008
Application Number:
20080032475
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer having a gradient of a silicon above and below the charge trap layer over the first insulator layer, and forming a second insulator layer over the charge trap layer.
MEMORY CELL SYSTEM WITH NITRIDE CHARGE ISOLATION
Granted: February 7, 2008
Application Number:
20080032464
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second insulator layer with the second intermediate layer.
MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS
Granted: January 31, 2008
Application Number:
20080023750
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS
Granted: January 31, 2008
Application Number:
20080023751
An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
MEMORY CELL SYSTEM WITH CHARGE TRAP
Granted: January 17, 2008
Application Number:
20080012060
A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
Granted: November 22, 2007
Application Number:
20070267686
A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
MEMORY SYSTEM WITH SWITCH ELEMENT
Granted: November 22, 2007
Application Number:
20070268744
A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.
Semiconductor memory device and manufacturing method thereof
Granted: November 15, 2007
Application Number:
20070262374
After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory…
Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions
Granted: November 15, 2007
Application Number:
20070262412
A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A…
SELF ALIGNED MEMORY ELEMENT AND WORDLINE
Granted: September 27, 2007
Application Number:
20070224724
An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells.…
MEMORY CELL SYSTEM USING SILICON-RICH NITRIDE
Granted: September 20, 2007
Application Number:
20070215932
A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.
