Semiconductor device
Granted: December 31, 2013
Patent Number:
8621643
A semiconductor device includes a nonvolatile memory, and an interface configured to transfer data to and from the nonvolatile memory. The interface includes a security logic unit which controls a security level for the data written to the nonvolatile memory, in accordance with a plurality of preset security codes and a lock code that is written to a specific area in the nonvolatile memory.
Output voltage controller, electronic device, and output voltage control method
Granted: December 31, 2013
Patent Number:
8618781
An output voltage controller includes a first controller which controls current supply to a inductor based on an output voltage, and a second controller which controls current supply to the inductor by controlling a period when an input end to which an input voltage is inputted, the inductor, and an output end from which the output voltage is outputted are coupled based on the input voltage.
Local interconnect having increased misalignment tolerance
Granted: December 31, 2013
Patent Number:
8617983
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect…
Void free interlayer dielectric
Granted: December 24, 2013
Patent Number:
8614475
A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
Processor system optimization supporting apparatus and supporting method
Granted: December 17, 2013
Patent Number:
8612805
In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the…
Semiconductor device and control method of the same
Granted: December 17, 2013
Patent Number:
8611167
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion…
Nonvolatile semiconductor storage device and data write method for the same
Granted: December 17, 2013
Patent Number:
8611160
A nonvolatile semiconductor storage device includes an identification code generating circuit, a simultaneous write bit count calculation circuit, a write range calculation circuit, and a program pulse generating circuit. The identification code generating circuit generates an identification code to be assigned to every one of bits to be written, and the simultaneous write bit count calculation circuit calculates the number of bits to be written simultaneously, the number being equalized…
Fabricating method of mirror bit memory device having split ONO film with top oxide film formed by oxidation process
Granted: December 17, 2013
Patent Number:
8610199
A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
Method of data transmission, data transmitting apparatus, and network system
Granted: December 10, 2013
Patent Number:
8605733
A method of data transmission that includes: transmitting first data to be transferred in a synchronous packet using a second asynchronous packet having priority higher than that of a first asynchronous packet; and requesting transmission of second data following the first data using the second asynchronous packet after a lapse of a certain time from the transmission of the second asynchronous packet.
Signal processor and communication device
Granted: December 10, 2013
Patent Number:
8605756
A signal processor includes a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller, configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of…
System and method for read data buffering wherein an arbitration policy determines whether internal or external buffers are given preference
Granted: December 3, 2013
Patent Number:
8601181
Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external…
Charging circuit
Granted: December 3, 2013
Patent Number:
8598851
A charging circuit that prevents a system abnormality caused by removal of a battery. The charging circuit includes a constant voltage charge controller which detects charge voltage and performs a constant voltage charging operation. A constant current charge controller detects charge current and performs a constant current charging operation. A controller controls the constant voltage charge controller to perform the constant voltage charging operation during a period from when the…
Semiconductor device and method for manufacturing the same
Granted: December 3, 2013
Patent Number:
8598717
A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.
Non-volatile FINFET memory array and manufacturing method thereof
Granted: December 3, 2013
Patent Number:
8598646
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the…
Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices
Granted: December 3, 2013
Patent Number:
8598005
A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and…
System and method for improving mesa width in a semiconductor device
Granted: December 3, 2013
Patent Number:
8598645
A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
Power supply device, control circuit, electronic device and control method for power supply
Granted: November 26, 2013
Patent Number:
8593126
A power supply device that includes a switch circuit to which an input voltage is supplied, a coil coupled between the switch circuit and an output terminal from which an output voltage is outputted. A voltage adding circuit adds a slope voltage to a reference voltage. A control unit compares a feedback voltage corresponding to the output voltage and the reference voltage and switches the switch circuit at a timing corresponding to a comparison result of the feedback voltage and the…
Semiconductor integrated circuit, operating method of semiconductor integrated circuit, and debug system
Granted: November 26, 2013
Patent Number:
8595562
A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution…
Pre-charge sensing scheme for non-volatile memory (NVM)
Granted: November 26, 2013
Patent Number:
8593881
The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a…
Voltage adjustment circuit and display device driving circuit
Granted: November 26, 2013
Patent Number:
8593447
A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data.
