HTO offset for long Leffective, better device performance
Granted: February 18, 2014
Patent Number:
8653581
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level…
Memory device and chip set processor pairing
Granted: February 11, 2014
Patent Number:
8650399
Systems, devices and/or methods that facilitate mutual authentication for processor and memory pairing are presented. A processor and a suitably equipped memory can be provided with a shared secret to facilitate mutual authentication. In addition, the memory can be configured to verify that the system operating instructions have not been subjected to unauthorized alterations. System integrity can be ensured according to the disclosed subject matter by mutual authentication of the…
Method for forming a semiconductor layer with improved gap filling properties
Granted: February 11, 2014
Patent Number:
8647969
A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
Electronic devices with ultraviolet blocking layers
Granted: February 4, 2014
Patent Number:
8643083
Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating…
Self-aligned STI with single poly for manufacturing a flash memory device
Granted: February 4, 2014
Patent Number:
8642441
A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners…
Method of manufacturing a semiconductor device
Granted: February 4, 2014
Patent Number:
8642422
In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are…
PLL circuit
Granted: January 28, 2014
Patent Number:
8638140
A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit,…
Signal descrambling detector
Granted: January 28, 2014
Patent Number:
8638931
Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The…
Apparatus and method for external charge pump on flash memory module
Granted: January 28, 2014
Patent Number:
8638633
A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.
Partial local self boosting for NAND
Granted: January 28, 2014
Patent Number:
8638609
A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word…
Control circuit for step-down and boost type switching supply circuit and method for switching supply circuit
Granted: January 28, 2014
Patent Number:
8638082
A control circuit for a switching supply, include: a first control circuit that selects one of a first signal to switch a boost mode and a step-down mode and a second signal to control an on-period of a switch based on an input voltage, the switch provided between a terminal to which the input voltage is applied and an inductor; and a second control circuit that controls the switching supply based on an output voltage and the selected one of the first signal and the second signal.
Semiconductor device and method of manufacturing the same
Granted: January 28, 2014
Patent Number:
8637997
The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the…
Semiconductor device and method for manufacturing thereof
Granted: January 28, 2014
Patent Number:
8637986
A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for…
Method and device employing polysilicon scaling
Granted: January 28, 2014
Patent Number:
8637918
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral…
Data writing method and system
Granted: January 21, 2014
Patent Number:
8635397
A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not…
Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant
Granted: January 21, 2014
Patent Number:
8633083
A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the…
Electrically programmable and erasable memory device and method of fabrication thereof
Granted: January 21, 2014
Patent Number:
8633074
The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
Image processing apparatus and method for image resizing matching data supply speed
Granted: January 14, 2014
Patent Number:
8630511
An image processing apparatus includes a data supply node to receive line data scanned in a main scan direction of an image, an image enlargement unit coupled to the data supply node to apply to the line data an enlargement process for enlarging the image by an enlargement factor equal to an integer so as to produce enlarged data at an output node, and an image reduction unit coupled to the output node of the image enlargement unit to apply to the enlarged data a reduction process for…
Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices
Granted: January 7, 2014
Patent Number:
8625353
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for…
Semiconductor device
Granted: December 31, 2013
Patent Number:
8621643
A semiconductor device includes a nonvolatile memory, and an interface configured to transfer data to and from the nonvolatile memory. The interface includes a security logic unit which controls a security level for the data written to the nonvolatile memory, in accordance with a plurality of preset security codes and a lock code that is written to a specific area in the nonvolatile memory.
