Chip positioning in multi-chip package
Granted: December 2, 2014
Patent Number:
8901756
Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a…
Semiconductor memory device having lowered bit line resistance
Granted: December 2, 2014
Patent Number:
8901637
A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of…
Semiconductor device sealed in a resin section and method for manufacturing the same
Granted: December 2, 2014
Patent Number:
8900993
A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar…
Semiconductor device and programming method
Granted: December 2, 2014
Patent Number:
8900928
The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a…
Method for forming narrow structures in a semiconductor device
Granted: December 2, 2014
Patent Number:
8901720
A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the…
Node system and supervisory node
Granted: November 25, 2014
Patent Number:
8897289
A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
Granted: November 25, 2014
Patent Number:
8896048
The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor…
Method for manufacturing a semiconductor device
Granted: November 25, 2014
Patent Number:
8895405
A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and…
Line-edge roughness improvement for small pitches
Granted: November 4, 2014
Patent Number:
8877641
A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional…
Switching regulator
Granted: November 4, 2014
Patent Number:
8878504
A switching regulator has an output circuit having first and second transistors and a connection node thereof as an output terminal; a switching control unit generating a first and second switching pulses for alternately switching the first and second transistors according to the load; and a first comparator monitoring an output voltage, and generating a pulse stopping control signal for stopping the generation of the switching pulses when the output voltage rises, and for generating the…
System and method for read data buffering wherein analyzing policy determines whether to decrement or increment the count of internal or external buffers
Granted: October 28, 2014
Patent Number:
8874810
Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication…
Self-aligned NAND flash select-gate wordlines for spacer double patterning
Granted: October 28, 2014
Patent Number:
8874253
A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein…
Data-processing method, program, and system
Granted: October 21, 2014
Patent Number:
8868822
A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector.
Non-Volatile memory with silicided bit line contacts
Granted: October 21, 2014
Patent Number:
8866213
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density…
Table lookup operation on masked data
Granted: October 7, 2014
Patent Number:
8855298
Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data.
Device and method for preventing lost synchronization
Granted: September 30, 2014
Patent Number:
8850257
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A…
Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
Granted: September 30, 2014
Patent Number:
8848452
Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying…
Method, apparatus, and manufacture for flash memory adaptive algorithm
Granted: September 23, 2014
Patent Number:
8842477
A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at…
Method of detecting an operating condition of an electric stepper motor
Granted: September 23, 2014
Patent Number:
8841874
An electrical stepper motor comprises a magnetical rotor and at least two electromagnetical driving coils for causing rotation of the rotator. A method of detecting an operating condition of the as e.g. a stall state of the electrical stepper motor comprises the steps of connecting one contact pin (P, M) of at least one of the electromagnetical driving coils via a high-impedance resistor (R1, R2) to a defined voltage source during a non-activated state of the driving coil, detecting a…
Spacer design to prevent trapped electrons
Granted: September 16, 2014
Patent Number:
8836012
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
