Data refresh in non-volatile memory
Granted: March 3, 2015
Patent Number:
8972652
A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing…
Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
Granted: February 24, 2015
Patent Number:
8966151
A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe…
For test (DFT) read speed through transition detector in built-in self-test (BIST) sort
Granted: February 24, 2015
Patent Number:
8964484
A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that…
Output switching circuit
Granted: February 17, 2015
Patent Number:
8957648
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating…
Memory device having trapezoidal bitlines and method of fabricating same
Granted: February 17, 2015
Patent Number:
8957472
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal…
Semiconductor device and method of fabrication
Granted: February 10, 2015
Patent Number:
8952536
A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by…
Soft error resistant circuitry
Granted: February 3, 2015
Patent Number:
8946663
An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound.
Method of forming controllably conductive oxide
Granted: February 3, 2015
Patent Number:
8946020
In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects…
Extending flash memory data retension via rewrite refresh
Granted: January 20, 2015
Patent Number:
8938655
Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional…
Bandgap voltage reference circuit
Granted: January 13, 2015
Patent Number:
8933682
A bandgap voltage reference circuit comprising: a first P-N junction circuit generating a first voltage which changes according to a first characteristic; a second P-N junction circuit generating a second voltage which changes according to a second characteristic different from the first characteristic; an amplifier receiving the first and second voltages at a pair of input terminals and changing the amount of an output current provided from a high-voltage power supply to an output…
Semiconductor device and voltage divider
Granted: January 6, 2015
Patent Number:
8928397
A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the…
Method for setting parameters and determining latency in a chained device system
Granted: January 6, 2015
Patent Number:
8930593
A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage…
Control circuit and electronic device
Granted: January 6, 2015
Patent Number:
8928177
A controller includes a difference detector that detects a difference between a switching timing of a first channel of a switching power supply including a plurality of channels, and a switching timing of a second channel of the switching power supply, the plurality of channels being coupled in common to an input power supply and performing switching operations in response to clock signals, and a timing adjuster that, based on a detection result of the difference detector, increases a…
Arithmetic logic unit architecture
Granted: December 30, 2014
Patent Number:
8924453
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a…
Oscillation circuit
Granted: December 30, 2014
Patent Number:
8922289
An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
Power control circuit performing soft start operation. power supply device, and electronic device
Granted: December 30, 2014
Patent Number:
8922181
A power control circuit includes a control circuit configured to perform a soft start operation before a power supply device performs a normal operation. The power control circuit also includes a counter circuit configured to divide a switching frequency of the power supply device in the normal operation, wherein the counter circuit measures a period of the soft start operation and when the period lasts for a set length, starts to divide the switching frequency, and wherein the power…
Exhaust system
Granted: December 23, 2014
Patent Number:
8915775
An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with…
Controlling the latchup effect
Granted: December 16, 2014
Patent Number:
8912014
A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.
Communication network device that compares first and second identification number of packet to determine if they are in conformance or non-conformance with self-ID packet
Granted: December 16, 2014
Patent Number:
8914554
A communication device including a comparison unit that compares a first identification number of which notification is provided by a packet that sequentially assigns identification numbers to a plurality of nodes in a network, and a second identification number, which is assigned to the communication device. A control unit notifies other nodes of the second identification number and that the identification number of the communication device has not been changed when the first…
Die seal layout for VFTL dual damascene in a semiconductor device
Granted: December 16, 2014
Patent Number:
8912093
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
