Continuous read burst support at high clock rates
Granted: August 12, 2014
Patent Number:
8806071
A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output…
Diode and resistive memory device structures
Granted: August 12, 2014
Patent Number:
8803120
In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.
Imaging device having a radiation detecting structure sensitive to neutron radiation
Granted: August 12, 2014
Patent Number:
8803066
An imaging device suitable for detecting certain imaging particles and recording the detection of imaging particles, and as such can include certain recording devices such as a charge storage structure.
System and method for improving reliability in a semiconductor device
Granted: August 12, 2014
Patent Number:
8802537
A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
Semiconductor manufacturing equipment and manufacturing method of the same
Granted: August 12, 2014
Patent Number:
8801895
A semiconductor manufacturing equipment includes a first chamber that has a first connection hole, a second chamber that has a second connection hole connected to the first connection hole of the first chamber, an O-ring that is provided between the first chamber and the second chamber so as to surround the first connection hole and the second connection hole, and a cover portion that covers a space between the first chamber and the second chamber.
Redundancy loading efficiency
Granted: August 5, 2014
Patent Number:
8799598
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions…
Flip chip bonded semiconductor device with shelf
Granted: August 5, 2014
Patent Number:
8796864
The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of…
Thermoelectric device for use with Stirling engine
Granted: August 5, 2014
Patent Number:
8793992
An exhaust gas manifold having thermoelectric devices in the exhaust manifold of a stirling engine is disclosed.
Planar cell ONO cut using in-situ polymer deposition and etch
Granted: July 29, 2014
Patent Number:
8790530
A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is…
Method of improving adhesion of dielectric cap to copper
Granted: July 29, 2014
Patent Number:
8790751
In a method of promoting adhesion between a copper body and a dielectric layer in contact therewith, the copper body and dielectric layer are placed in a vacuum chamber, in a chamber, the copper body and dielectric layer within the chamber are heated, and SiH4 is provided in the chamber.
Device having multiple wire bonds for a bond area and methods thereof
Granted: July 29, 2014
Patent Number:
8791007
Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
Method of depositing copper using physical vapor deposition
Granted: July 29, 2014
Patent Number:
8791018
The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.
Data commit on multicycle pass complete without error
Granted: July 22, 2014
Patent Number:
8788740
A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction…
Semiconductor device and method of controlling the same
Granted: July 22, 2014
Patent Number:
8787089
An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this…
Reference voltage circuit and semiconductor integrated circuit
Granted: July 22, 2014
Patent Number:
8786358
A reference voltage circuit includes a first amplifier configured to output a reference voltage, a second amplifier coupled to the first amplifier, an offset adjustment voltage generation circuit, a first load device and a first pn junction device, and second and third load devices and a second pn junction device. The offset adjustment voltage generation circuit is configured to generate a voltage which is input to the third and fourth input terminals of the second amplifier, and reduce…
Non-volatile FINFET memory device and manufacturing method thereof
Granted: July 22, 2014
Patent Number:
8785275
Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type…
Memory system with Fin FET technology
Granted: July 22, 2014
Patent Number:
8785268
A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
Semiconductor memory device featuring selective data storage in a stacked memory cell structure
Granted: July 8, 2014
Patent Number:
8773885
A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that…
Device and method for preventing lost synchronization
Granted: July 8, 2014
Patent Number:
8775853
A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the…
Method for protecting data against differntial fault analysis involved in rivest, shamir, and adleman cryptography using the chinese remainder theorem
Granted: July 8, 2014
Patent Number:
8774400
Systems and methods for effectively protecting data against differential fault analysis involved in Rivest, Shamir, and Adleman (“RSA”) cryptography using the Chinese Remainder Theorem (“CRT”) are described herein. A CRT RSA component facilitates modular exponentiation of a received message, and a verification component reconstructs the received message. An exponentiation component performs a first modular exponentiation and a second modular exponentiation of the received…