Synopsys Patent Applications

POWER HARVESTING FOR INTEGRATED CIRCUITS

Granted: October 5, 2017
Application Number: 20170287977
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…

CUSTOM LAYOUT OF INTEGRATED CIRCUIT (IC) DESIGNS

Granted: October 5, 2017
Application Number: 20170286584
Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a graphical user interface (GUI) of the IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of the device contacts so that the diffusion region is aligned with…

Method for Testing computer program product

Granted: September 28, 2017
Application Number: 20170277890
This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to…

IMAGE PROCESSING METHOD

Granted: August 31, 2017
Application Number: 20170249529
A computer-implemented image processing technique for selectively recovering the features of an original CAD model after the original CAD model has been converted to a digitized image and a new CAD model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing under governance of a programmed processor so as to recover accuracy and reintroduce feature edges and feature corners as well as other detailed…

Layer Class Relative Density for Technology Modeling in IC Technology

Granted: August 10, 2017
Application Number: 20170228492
A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.

3D RESIST PROFILE AWARE RESOLUTION ENHANCEMENT TECHNIQUES

Granted: August 3, 2017
Application Number: 20170220723
Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

Tined Gate to Control Threshold Voltage in a Device Formed of Materials Having Piezoelectric Properties

Granted: June 29, 2017
Application Number: 20170186860
Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least…

POWER-AWARE DYNAMIC ENCODING

Granted: June 1, 2017
Application Number: 20170154132
Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression,…

ANNOTATING ISOLATED SIGNALS

Granted: May 25, 2017
Application Number: 20170147720
Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a…

TOPOGRAPHY SIMULATION OF ETCHING AND/OR DEPOSITION ON A PHYSICAL STRUCTURE

Granted: May 25, 2017
Application Number: 20170147724
Systems and techniques are described for topography simulation of etching and/or deposition on a physical structure. The structural information can be represented using a three-dimensional (3D) voxel grid data structure. For each particle emitted by a Monte-Carlo particle emission model, a topographical modification caused by the particle can be determined by (1) calculating fluxes, (2) evaluating surface reactions, and (3) modifying the physical structure. The effect of the etching…

ATOMIC STRUCTURE OPTIMIZATION

Granted: May 4, 2017
Application Number: 20170124293
Electronic design automation modules simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.

ALTERNATIVE HIERARCHICAL VIEWS OF A CIRCUIT DESIGN

Granted: March 30, 2017
Application Number: 20170091367
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the…

METHOD TO APPROXIMATE CHEMICAL POTENTIAL IN A TERNARY OR QUATERNARY SEMICONDUCTOR

Granted: March 23, 2017
Application Number: 20170083644
Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example III-V semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group III element and each group V element. The first relationship relates total energy of a defect-free system to the sum, over all of the group III and group V elements, of…

IDENTIFYING FAILURE MECHANISMS BASED ON A POPULATION OF SCAN DIAGNOSTIC REPORTS

Granted: February 23, 2017
Application Number: 20170052861
Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. The failure mechanisms can be identified based on the topic distributions for the portions of the scan diagnostic reports and the feature distributions for the…

ACCURATE GLITCH DETECTION

Granted: February 23, 2017
Application Number: 20170053051
Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when…

Pre-Silicon Design Rule Evaluation

Granted: February 9, 2017
Application Number: 20170039308
Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior…

2D MATERIAL SUPER CAPACITORS

Granted: February 9, 2017
Application Number: 20170040411
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…

Identifying Software Components in a Software Codebase

Granted: February 2, 2017
Application Number: 20170032117
Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a…

Methods for Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature

Granted: January 26, 2017
Application Number: 20170025496
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…

POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS

Granted: January 19, 2017
Application Number: 20170017746
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG…