BUFFER CIRCUITRY FOR STORE TO LOAD FORWARDING
Granted: March 28, 2024
Application Number:
20240103761
A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is…
ON-CHIP AUTOMATION OF CLOCK-TO-Q ACCESS TIME MEASUREMENT OF A MEMORY DEVICE
Granted: November 2, 2023
Application Number:
20230352069
An integrated circuit (IC) may include a memory device and a circuit coupled with the memory device. The circuit may precondition the memory device to sustain oscillations, initiate first oscillations in a first loop that includes the memory device, and initiate second oscillations in a second loop that does not include the memory device.
EXTENDED REGULAR EXPRESSION MATCHING IN A DIRECTED ACYCLIC GRAPH BY USING ASSERTION SIMULATION
Granted: July 6, 2023
Application Number:
20230214574
A directed acyclic graph (DAG) and an extended regular expression (ERE) may be received. A circuit design may be generated based on the DAG. A cover property may be generated based on the ERE. The circuit design may be simulated. A first result may be determined based on whether the cover property is satisfied during the simulating the circuit design. It may be determined whether the ERE matches a path in the DAG based on the first result.
FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIRCUIT COMPONENTS
Granted: May 18, 2023
Application Number:
20230154751
A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer…
MEMORY OPTIMIZATION FOR STORING OBJECTS IN NESTED HASH MAPS USED IN ELECTRONIC DESIGN AUTOMATION SYSTEMS
Granted: March 2, 2023
Application Number:
20230065867
Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which…
UNIFIED POWER FORMAT ANNOTATED RTL IMAGE RECOGNITION TO ACCELERATE LOW POWER VERIFICATION CONVERGENCE
Granted: February 9, 2023
Application Number:
20230043751
A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design…
UNIFIED POWER FORMAT ANNOTATED RTL IMAGE RECOGNITION TO ACCELERATE LOW POWER VERIFICATION CONVERGENCE
Granted: February 9, 2023
Application Number:
20230043751
A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design…
INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHNOLOGY
Granted: January 26, 2023
Application Number:
20230023073
An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set…
INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHNOLOGY
Granted: January 26, 2023
Application Number:
20230023073
An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set…
DIAGNOSIS OF INCONSISTENT CONSTRAINTS IN A POWER INTENT FOR AN INTEGRATED CIRCUIT DESIGN
Granted: January 19, 2023
Application Number:
20230016865
A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where…
DIAGNOSIS OF INCONSISTENT CONSTRAINTS IN A POWER INTENT FOR AN INTEGRATED CIRCUIT DESIGN
Granted: January 19, 2023
Application Number:
20230016865
A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where…
SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP
Granted: January 5, 2023
Application Number:
20230005562
A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer…
DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING
Granted: January 5, 2023
Application Number:
20230004698
A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final…
D-TYPE WHOLLY DISSIMILAR HIGH-SPEED STATIC SET-RESET FLIP FLOP
Granted: December 15, 2022
Application Number:
20220399881
A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a…
FAIL-SAFE SOFTWARE ACCESS LICENSING CONTROL ON A PER PROJECT BASIS WITHOUT A PRIORI KNOWLEDGE OF PROJECT DETAILS
Granted: December 8, 2022
Application Number:
20220391477
A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.
AUTOMATION FOR FUNCTIONAL SAFETY DIAGNOSTIC COVERAGE
Granted: November 17, 2022
Application Number:
20220366120
A method of implementing an automated technology for conducting functional safety (FuSa) diagnostic coverage is provided. The method can include receiving functional safety information that includes failure modes defining wrong values of a signal indicating a factor manifesting an error, receiving an identification of internal safety protected signals and a diagnostic coverage for the FuSa block, performing back tracing of possible paths for an output port of a FuSa block for each…
LAYOUT VERSUS SCHEMATIC (LVS) DEVICE EXTRACTION USING PATTERN MATCHING
Granted: November 3, 2022
Application Number:
20220350950
A method includes obtaining a target integrated circuit (IC) layout, accessing a repository, identifying a device within the target IC layout by matching an area of the target IC layout to a source pattern, and replacing at least a portion of the area of the target IC layout with a replacement pattern. The repository stores the source pattern for the device and the replacement pattern corresponding to the source pattern.
REAL TIME VIEW SWAPPING (RTVS) IN A MIXED SIGNAL SIMULATION
Granted: October 13, 2022
Application Number:
20220327272
A method, a system, and a non-transitory computer readable medium for simulating a circuit are provided. The method includes generating a digital simulation file for the circuit that includes a block, generating a mixed simulation file for the circuit, generating a waveform file by executing the digital simulation file for a first time window of a simulation, determining a plurality of analog values for the block based on the waveform file, and executing, by a processor, the mixed…
GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY
Granted: October 13, 2022
Application Number:
20220327266
A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.
RUNTIME AND MEMORY EFFICIENT ATTRIBUTE QUERY HANDLING FOR DISTRIBUTED ENGINE
Granted: October 6, 2022
Application Number:
20220318481
A method, a system, and a non-transitory computer readable medium are provided. The method includes performing, by one or more computing devices, a lookahead scan of a file of a circuit design to extract information associated with a query in an iterative loop, performing an action to retrieve attribute information from one or more partitions of the circuit design before executing the iterative loop, and querying the iterative loop using the stored attribute information. The action…
