CONTROL SET OPTIMIZATION FOR CIRCUIT DESIGNS BY DETECTION OF REGISTERS WITH REDUNDANT RESETS
Granted: March 6, 2025
Application Number:
20250077760
Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by…
LOW-SKEW SOLUTIONS FOR LOCAL CLOCK NETS IN INTEGRATED CIRCUITS
Granted: March 6, 2025
Application Number:
20250077757
Generating low skew clock solutions for local clocks in an integrated circuit includes, for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net. Each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay. The upper bound delays of the plurality of delay ranges are allocated as setup constraints for the respective clock pins of the local clock net. The lower bound delays are allocated as hold…
MEASURING AND COMPENSATING FOR CLOCK TREE VARIATION
Granted: February 6, 2025
Application Number:
20250044827
A system for clock variation measurement includes a first clock counter circuit configured to generate a plurality of first counts of a first clock signal, a second clock counter circuit configured to generate a plurality of second counts of a second clock signal, a first synchronizer circuit configured to synchronize the plurality of first counts according to a third clock signal, and a second synchronizer circuit configured to synchronize the plurality of second counts according to the…
SYSTEMS AND METHODS FOR MACHINE LEARNING BASED VOLTAGE DROP PREDICTION FOR A 3D STACKED DEVICE
Granted: January 30, 2025
Application Number:
20250036848
A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each…
SYSTEMS AND METHODS FOR MEMORY MANAGEMENT
Granted: January 2, 2025
Application Number:
20250004941
A computer-implemented method for memory management can include identifying a set of one or more memory blocks of virtual memory to be allocated for storage of a content into a plurality of memory banks that subdivide physical memory. The method can include storing the content in the set of one or more memory blocks of virtual memory. The method can include assigning an identifier to the set of one or more memory blocks of virtual memory that store the content. The method can include…
SYSTEMS AND METHODS FOR MANAGING CHANNEL ACCESSIBILITY
Granted: January 2, 2025
Application Number:
20250007684
A computer-implemented method for managing channel accessibility can include detecting, by a first circuit, a transmit request from the first circuit to transmit a message into a communication channel connecting the first circuit to second circuit. The method can include determining, by the first circuit, whether to approve the transmit request based on an evaluation of a first number associated with messages previously transmitted by the first circuit to the second circuit over the…
SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY
Granted: January 2, 2025
Application Number:
20250005249
Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the…
COMPILING A TENSOR TILING SPECIFICATION TO MULTI-DIMENSIONAL DATA MOVER CIRCUIT CONFIGURATIONS
Granted: January 2, 2025
Application Number:
20250005246
Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the…
TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
Granted: January 2, 2025
Application Number:
20250004983
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a…
MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER
Granted: January 2, 2025
Application Number:
20250004961
A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client…
HIGH PERFORMANCE TRACE OFFLOAD CIRCUIT ARCHITECTURE
Granted: January 2, 2025
Application Number:
20250004919
An integrated circuit includes a compute circuit and a trace data mover circuit coupled to the compute circuit. The trace data mover circuit is configured to convey trace data generated by the compute circuit to a destination circuit. The trace data mover circuit includes a controller circuit configured to receive a stream of trace data from the compute circuit and generate instructions for writing the trace data. The trace data mover circuit includes a writer circuit configured to write…
SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING
Granted: January 2, 2025
Application Number:
20250004782
A computer-implemented method for managing processing order for a plurality of commands can include in response to receiving each command of a plurality of commands in a receipt order, assigning each respective command of the plurality of commands to a respective processing queue of a plurality of processing queues to be processed, and setting, for each of the plurality of commands and in the receipt order, an identifier based on the respective queue assigned to each of the plurality of…
SYNTHESIS OF SIMULATION-DIRECTED STATEMENTS
Granted: December 19, 2024
Application Number:
20240419878
A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit…
PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM
Granted: December 19, 2024
Application Number:
20240419626
Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels…
MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE
Granted: December 12, 2024
Application Number:
20240413099
Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and…
HIGH-LEVEL SYNTHESIS OF DESIGNS USING LOOP-AWARE EXECUTION INFORMATION
Granted: December 12, 2024
Application Number:
20240411967
High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of…
SELF-AUTHENTICATION OF DATA STORED OFF-CHIP
Granted: December 5, 2024
Application Number:
20240406001
Methods and circuit arrangements for self-authentication of a data set by circuitry on a semi-conductor die include export circuitry and a non-volatile memory disposed on the semiconductor die. The export circuitry is configured to generate a public-private key pair and generate a signature from a data set and a private key of the key pair. The export circuitry is configured to store a version of a public key of the key pair in the non-volatile memory, destroy the private key, and output…
GLOBAL PLACEMENT OF CIRCUIT DESIGNS USING A CALIBRATED SIMPLE TIMER
Granted: November 28, 2024
Application Number:
20240394453
A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at…
SELF-RELIANT SMARTNICS
Granted: November 21, 2024
Application Number:
20240385983
Embodiments herein describe a self-reliant Network Interface Controller (NIC) that can perform the maintenance and control operations part of performing a distributed computation which relies on data received from multiple peers (or nodes) that are connected by a network. Rather than a CPU-driven adaptive compute where the CPU(s) in a host perform maintenance and control operations, the embodiments herein shift these operations to the NIC. The NIC can perform control operations such as…
HARDWARE EVENT TRACE WINDOWING FOR A DATA PROCESSING ARRAY
Granted: November 14, 2024
Application Number:
20240378358
Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user…
