Xilinx Patent Applications

SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN TOPOLOGY

Granted: October 5, 2017
Application Number: 20170287919
Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.

HALF-RATE INTEGRATING DECISION FEEDBACK EQUALIZATION WITH CURRENT STEERING

Granted: September 14, 2017
Application Number: 20170264467
Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential…

LINEAR GAIN CODE INTERLEAVED AUTOMATIC GAIN CONTROL CIRCUIT

Granted: August 24, 2017
Application Number: 20170244371
An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the…

CHIP PACKAGE ASSEMBLY WITH POWER MANAGEMENT INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT DIE

Granted: August 17, 2017
Application Number: 20170236809
A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that…

SYSTEM-LEVEL INTERCONNECT RING FOR A PROGRAMMABLE INTEGRATED CIRCUIT

Granted: August 3, 2017
Application Number: 20170220508
An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit…

ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE

Granted: August 3, 2017
Application Number: 20170220509
An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package…

CHANNEL SELECTION IN MULTI-CHANNEL SWITCHING NETWORK

Granted: July 20, 2017
Application Number: 20170207998
Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the…

HARDWARE POWER-ON INITIALIZATION OF AN SOC THROUGH A DEDICATED PROCESSOR

Granted: June 15, 2017
Application Number: 20170168841
In an example, a system-on-chip (SoC) includes a hardware power-on-reset (POR) sequencer circuit coupled to a POR pin. The SoC further includes a platform management unit (PMU) circuit, coupled to the hardware POR sequencer circuit, the PMU including one or more central processing units (CPUs) and a read only memory (ROM). The SoC further includes one or more processing units configured to execute a boot process. The hardware POR sequencer circuit is configured to initialize the PMU. The…

FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN

Granted: June 8, 2017
Application Number: 20170161419
Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the…

METHOD FOR INCREASING ACTIVE INDUCTOR OPERATING RANGE AND PEAKING GAIN

Granted: May 11, 2017
Application Number: 20170134009
Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable…

MULTISTAGE BOOT IMAGE LOADING BY CONFIGURATION OF A BUS INTERFACE

Granted: May 4, 2017
Application Number: 20170123815
An integrated circuit (IC) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the IC. Using the bus interface module, a second boot image is received from the memory of the…

METHODS AND CIRCUITS FOR DEBUGGING CIRCUIT DESIGNS

Granted: April 27, 2017
Application Number: 20170115348
Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to…

INTERPOSER-LESS STACK DIE INTERCONNECT

Granted: April 20, 2017
Application Number: 20170110407
Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal…

DIRECT MEMORY ACCESS FOR PROGRAMMABLE LOGIC DEVICE CONFIGURATION

Granted: April 6, 2017
Application Number: 20170097910
Using a storage interface circuit of a programmable IC, a first set of configuration data can be communicated between a storage circuit and the programmable IC. Using the first set of configuration data, the programmable IC can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module…

INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS

Granted: April 6, 2017
Application Number: 20170098024
A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the…

STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID

Granted: March 30, 2017
Application Number: 20170092619
A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards…

TRANSMITTER CIRCUIT FOR AND METHODS OF GENERATING A MODULATED SIGNAL IN A TRANSMITTER

Granted: March 2, 2017
Application Number: 20170063580
A transmitter circuit for generating a modulated signal in a transmitter of an integrated circuit is described. The transmitter circuit comprises a multiplexing stage having a multiplexing circuit configured to receive a differential input signal and to generate a differential output signal at a first output node of a first current path and at a second output node of a second current path, the multiplexing stage having a gain circuit configured to increase the swing of the differential…

OFFSET INSENSITIVE QUADRATURE CLOCK ERROR CORRECTION AND DUTY CYCLE CALIBRATION FOR HIGH-SPEED CLOCKING

Granted: February 2, 2017
Application Number: 20170033774
Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the…

CIRCUITS FOR AND METHODS OF GENERATING A MODULATED SIGNAL IN A TRANSMITTER

Granted: January 19, 2017
Application Number: 20170019278
A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path;…

METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS

Granted: January 12, 2017
Application Number: 20170012041
An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.