SWITCHING BETWEEN REDUNDANT AND NON-REDUNDANT MODES OF SOFTWARE EXECUTION
Granted: April 11, 2024
Application Number:
20240118901
Executing critical and non-critical sections of program code include executing a non-critical section of a first program by a first processor and executing a non-critical section of a second program by a second processor. The first processor signals the second processor with context to commence redundant execution of the critical section. The second processor switches from executing the second program to executing the critical section of the first program. The first processor executes…
MULTIPLIER BLOCK FOR BLOCK FLOATING POINT AND FLOATING POINT VALUES
Granted: April 11, 2024
Application Number:
20240118868
A mode control circuit operates a circuit arrangement in either a first mode to multiply floating point operands or a second mode to compute a dot product of two vectors of block floating point values. A block of multiplier circuits generates products from first pairs of p-terms. Each p-term is a portion of a significand of one of the floating point operands when operating in the first mode, or a significand of one of the block floating point values when operating in the second mode. An…
SATISFYING CIRCUIT DESIGN CONSTRAINTS USING A COMBINATION OF MACHINE LEARNING MODELS
Granted: April 4, 2024
Application Number:
20240111932
Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the…
IMPLEMENTING DATA FLOWS OF AN APPLICATION ACROSS A MEMORY HIERARCHY OF A DATA PROCESSING ARRAY
Granted: March 21, 2024
Application Number:
20240094944
Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object…
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
Granted: March 14, 2024
Application Number:
20240088900
An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus…
INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING ARRAY AND MICROCONTROLLER
Granted: February 29, 2024
Application Number:
20240069511
Instruction generation for a data processing array and microcontroller includes generating a tensor-level intermediate representation from a machine learning model using kernel expressions. Statements of the tensor-level intermediate representation are partitioned into a first set of statements and a second set of statements. From the first set of statements, kernel instructions are generated based on a reconfigurable neural engine model. The kernel instructions are executable by a…
FRACTIONAL LOGARITHMIC NUMBER SYSTEM ADDER
Granted: February 29, 2024
Application Number:
20240069865
An adder for fractional logarithmic number system (FLNS) format operands includes a compare-and-swap circuit that inputs first and second FLNS operands represented by fixed point values and provides a greater one as operand x and a lesser or equal one as operand y. Sign bits are sx and sy of x and y, respectively, qx and qy, are integer portions of x and y, respectively, fraction portions of x and y have integer values rx and ry, respectively. The compare-and-swap circuit is configured…
SOFTMAX AND LOG SOFTMAX METHOD AND SYSTEM
Granted: February 22, 2024
Application Number:
20240061903
Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases…
INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL
Granted: February 8, 2024
Application Number:
20240045692
Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions…
LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE
Granted: February 8, 2024
Application Number:
20240046015
Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO…
INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL
Granted: February 8, 2024
Application Number:
20240045692
Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions…
LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE
Granted: February 8, 2024
Application Number:
20240046015
Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO…
RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHITECTURE
Granted: January 25, 2024
Application Number:
20240028556
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHITECTURE
Granted: January 25, 2024
Application Number:
20240028556
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
COMPILER-BASED GENERATION OF TRANSACTION ACCURATE MODELS FROM HIGH-LEVEL LANGUAGES
Granted: January 11, 2024
Application Number:
20240012629
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that…
WAVEFORM STIMULUS GENERATION
Granted: January 11, 2024
Application Number:
20240012973
Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according…
WAVEFORM STIMULUS GENERATION
Granted: January 11, 2024
Application Number:
20240012973
Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according…
COMPILER-BASED GENERATION OF TRANSACTION ACCURATE MODELS FROM HIGH-LEVEL LANGUAGES
Granted: January 11, 2024
Application Number:
20240012629
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that…
CACHED SYSTEM FOR MANAGING STATE VECTORS
Granted: January 4, 2024
Application Number:
20240004794
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.
3D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY
Granted: January 4, 2024
Application Number:
20240005074
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.
