SYSTEMS AND METHODS FOR MANAGING CHANNEL ACCESSIBILITY
Granted: January 2, 2025
Application Number:
20250007684
A computer-implemented method for managing channel accessibility can include detecting, by a first circuit, a transmit request from the first circuit to transmit a message into a communication channel connecting the first circuit to second circuit. The method can include determining, by the first circuit, whether to approve the transmit request based on an evaluation of a first number associated with messages previously transmitted by the first circuit to the second circuit over the…
SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY
Granted: January 2, 2025
Application Number:
20250005249
Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the…
SYNTHESIS OF SIMULATION-DIRECTED STATEMENTS
Granted: December 19, 2024
Application Number:
20240419878
A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit…
PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM
Granted: December 19, 2024
Application Number:
20240419626
Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels…
MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE
Granted: December 12, 2024
Application Number:
20240413099
Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and…
HIGH-LEVEL SYNTHESIS OF DESIGNS USING LOOP-AWARE EXECUTION INFORMATION
Granted: December 12, 2024
Application Number:
20240411967
High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of…
SELF-AUTHENTICATION OF DATA STORED OFF-CHIP
Granted: December 5, 2024
Application Number:
20240406001
Methods and circuit arrangements for self-authentication of a data set by circuitry on a semi-conductor die include export circuitry and a non-volatile memory disposed on the semiconductor die. The export circuitry is configured to generate a public-private key pair and generate a signature from a data set and a private key of the key pair. The export circuitry is configured to store a version of a public key of the key pair in the non-volatile memory, destroy the private key, and output…
GLOBAL PLACEMENT OF CIRCUIT DESIGNS USING A CALIBRATED SIMPLE TIMER
Granted: November 28, 2024
Application Number:
20240394453
A design tool calibrates current delays of timing arcs in a current placement of a circuit design by determining respective delta-delays of the timing arcs. The current placement is represented by timing nodes connected by the timing arcs in a graph. The calibrating is based on a first timer model indicating arrival times at the timing nodes based on timing propagation without accounting for timing exceptions, and a reference timer indicating slacks that account for timing exceptions at…
SELF-RELIANT SMARTNICS
Granted: November 21, 2024
Application Number:
20240385983
Embodiments herein describe a self-reliant Network Interface Controller (NIC) that can perform the maintenance and control operations part of performing a distributed computation which relies on data received from multiple peers (or nodes) that are connected by a network. Rather than a CPU-driven adaptive compute where the CPU(s) in a host perform maintenance and control operations, the embodiments herein shift these operations to the NIC. The NIC can perform control operations such as…
HARDWARE EVENT TRACE WINDOWING FOR A DATA PROCESSING ARRAY
Granted: November 14, 2024
Application Number:
20240378358
Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user…
DATA PROCESSING ARRAY EVENT TRACE AND PROFILING USING PROCESSOR SYSTEM EXECUTED KERNELS
Granted: November 14, 2024
Application Number:
20240378062
Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data…
RING MODULATORS WITH LOW-LOSS AND LARGE FREE SPECTRAL RANGE (FSR) ON A SILICON-ON-INSULATOR (SOI) PLATFORM
Granted: November 7, 2024
Application Number:
20240369864
A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be…
PREDICTION OF ROUTING CONGESTION
Granted: October 31, 2024
Application Number:
20240362393
A congestion prediction machine learning model is trained to generate, prior to placement, a prediction value indicative of a congestion level likely to result from placement and routing of a netlist based on features of the netlist. In response to the prediction value indicating the congestion level is greater than a threshold, a design tool determines an implementation-flow action and performs the implementation-flow action to generate implementation data that is suitable for making an…
DYNAMIC MEMORY ALLOCATION IN PROBING SIGNAL STATES
Granted: October 24, 2024
Application Number:
20240354478
Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected…
DATA PROCESSING ARRAY EVENT TRACE CUSTOMIZATION, OFFLOAD, AND ANALYSIS
Granted: October 24, 2024
Application Number:
20240354223
Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one…
ALIGNING MULTI-CHIP DEVICES
Granted: October 17, 2024
Application Number:
20240346220
Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be…
DETERMINISTIC RESET MECHANISM FOR ASYNCHRONOUS GEARBOX FIFOS FOR PREDICTABLE LATENCY
Granted: October 3, 2024
Application Number:
20240329924
Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon…
DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS
Granted: October 3, 2024
Application Number:
20240330191
Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer…
HIGH-SPEED DEBUG PORT TRACE CIRCUIT
Granted: October 3, 2024
Application Number:
20240330145
An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit…
HIGH-SPEED OFFLOADING OF TRACE DATA FROM AN INTEGRATED CIRCUIT
Granted: October 3, 2024
Application Number:
20240330144
Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace…
