SOFTWARE DEFINED SUBSYSTEM CREATION FOR HETEROGENEOUS INTEGRATED CIRCUITS
Granted: May 20, 2021
Application Number:
20210150072
Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable…
POWER DELIVERY NETWORK FOR ACTIVE-ON-ACTIVE STACKED INTEGRATED CIRCUITS
Granted: May 13, 2021
Application Number:
20210143127
An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs…
SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIVE SYSTEM
Granted: April 29, 2021
Application Number:
20210124711
An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
TRACING STATUS OF A PROGRAMMABLE DEVICE
Granted: March 18, 2021
Application Number:
20210081215
Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.
DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRATED CIRCUIT
Granted: February 11, 2021
Application Number:
20210042252
A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically…
NETWORK INTERFACE DEVICE AND HOST PROCESSING DEVICE
Granted: January 28, 2021
Application Number:
20210026689
A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected,…
METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR PROCESSING DATA
Granted: January 14, 2021
Application Number:
20210014343
Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful, the data made available to the application is committed.
ROOT MONITORING ON AN FPGA USING SATELLITE ADCS
Granted: January 14, 2021
Application Number:
20210011172
Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and…
LEARNING NEURAL NETWORKS OF PROGRAMMABLE DEVICE BLOCKS DIRECTLY WITH BACKPROPAGATION
Granted: December 24, 2020
Application Number:
20200401882
An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.
HYBRID HARDWARE-SOFTWARE COHERENT FRAMEWORK
Granted: December 3, 2020
Application Number:
20200379664
Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The…
COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE
Granted: November 26, 2020
Application Number:
20200372200
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels…
HARDWARE-SOFTWARE DESIGN FLOW FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
Granted: November 26, 2020
Application Number:
20200372123
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on…
FLOW CONVERGENCE DURING HARDWARE-SOFTWARE DESIGN FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
Granted: November 26, 2020
Application Number:
20200371787
For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not…
DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM
Granted: November 26, 2020
Application Number:
20200371761
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the…
HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
Granted: November 26, 2020
Application Number:
20200371759
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS…
DUAL-DRIVER INTERFACE
Granted: November 19, 2020
Application Number:
20200364167
A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel…
MACHINE LEARNING MODEL UPDATES TO ML ACCELERATORS
Granted: October 29, 2020
Application Number:
20200341941
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators…
NETWORK INTERFACE DEVICE
Granted: October 29, 2020
Application Number:
20200344180
A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.
INTEGRATED CIRCUIT DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION
Granted: October 29, 2020
Application Number:
20200343237
Disclosed herein are integrated circuit devices and and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad…
MULTI-CHIP STRUCTURE INCLUDING A MEMORY DIE STACKED ON DIE HAVING PROGRAMMABLE INTEGRATED CIRCUIT
Granted: October 29, 2020
Application Number:
20200343234
Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first…
