Network Interface Device and Method
Granted: October 22, 2020
Application Number:
20200336312
A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.
PERIPHERAL I/O DEVICE WITH ASSIGNABLE I/O AND COHERENT DOMAINS
Granted: October 15, 2020
Application Number:
20200327089
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent…
APPARATUS AND METHOD TO REDUCE LOCK TIME VIA FREQUENCY BAND CALIBRATION
Granted: September 24, 2020
Application Number:
20200304130
Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each…
PACKAGE INTEGRATION FOR MEMORY DEVICES
Granted: September 24, 2020
Application Number:
20200303341
An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy…
LOCKING EXECUTION OF CORES TO LICENSED PROGRAMMABLE DEVICES IN A DATA CENTER
Granted: September 17, 2020
Application Number:
20200293636
An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to…
LOCKING EXECUTION OF CORES TO LICENSED PROGRAMMABLE DEVICES IN A DATA CENTER
Granted: September 17, 2020
Application Number:
20200293635
An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist,…
CIRCUITS FOR AND METHODS OF CALIBRATING A CIRCUIT IN AN INTEGRATED CIRCUIT DEVICE
Granted: September 17, 2020
Application Number:
20200293080
A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second…
METHOD AND APPARATUS FOR A PHASE LOCKED LOOP CIRCUIT
Granted: September 10, 2020
Application Number:
20200287551
A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to…
Network Interface Device
Granted: August 27, 2020
Application Number:
20200274827
Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of…
Network Interface Device
Granted: August 27, 2020
Application Number:
20200274921
A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst…
BOUNDARY LOGIC INTERFACE
Granted: August 27, 2020
Application Number:
20200274536
Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements.…
CONFIGURING PROGRAMMABLE LOGIC REGION VIA PROGRAMMABLE NETWORK
Granted: August 20, 2020
Application Number:
20200264901
Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the…
RETAINING MEMORY DURING PARTIAL RECONFIGURATION
Granted: July 30, 2020
Application Number:
20200241770
Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can…
System and Apparatus for Providing Network Security
Granted: July 2, 2020
Application Number:
20200213364
A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.
PHASE NOISE COMPENSATION IN DIGITAL BEAMFORMING RADAR SYSTEMS
Granted: June 18, 2020
Application Number:
20200191937
A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of…
INTEGRATED CIRCUITS AND METHODS TO ACCELERATE DATA QUERIES
Granted: June 11, 2020
Application Number:
20200183937
Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may…
Encapsulated Accelerator
Granted: June 4, 2020
Application Number:
20200174954
A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the…
HIGH DENSITY SUBSTRATE AND STACKED SILICON PACKAGE ASSEMBLY HAVING THE SAME
Granted: May 21, 2020
Application Number:
20200161229
An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a…
PROGRAMMING AND CONTROLLING COMPUTE UNITS IN AN INTEGRATED CIRCUIT
Granted: May 21, 2020
Application Number:
20200159680
An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in…
STREAMING PLATFORM FLOW AND ARCHITECTURE
Granted: May 14, 2020
Application Number:
20200153756
A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged…
