POWER DISTRIBUTION FOR ACTIVE-ON-ACTIVE DIE STACK WITH REDUCED RESISTANCE
Granted: August 22, 2019
Application Number:
20190259702
Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack…
HIGH DENSITY ROUTING FOR HETEROGENEOUS PACKAGE INTEGRATION
Granted: August 22, 2019
Application Number:
20190259695
A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
METHOD OF SELECTING ROUTING RESOURCES IN A MULTI-CHIP INTEGRATED CIRCUIT DEVICE
Granted: August 22, 2019
Application Number:
20190258767
A method of selecting routing resources in a multi-chip integrated circuit device is described. The method comprises placing a design on the multi-chip integrated circuit device; estimating a number of vias required to enable connections between chips of the multi-chip integrated circuit device that is placed with a portion of the design; identifying an area of a chip having a number of vias that is greater than a maximum number of vias for the area of the chip; selecting a partition…
MEMORY SUBSYSTEM FOR SYSTEM-ON-CHIP
Granted: August 15, 2019
Application Number:
20190250853
Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory…
CUSTOMIZABLE MULTI QUEUE DMA INTERFACE
Granted: August 8, 2019
Application Number:
20190243781
Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic…
END-TO-END QUALITY-OF-SERVICE IN A NETWORK-ON-CHIP
Granted: August 1, 2019
Application Number:
20190238453
An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.
ISOLATION ENHANCEMENT WITH ON-DIE SLOT-LINE ON POWER/GROUND GRID STRUCTURE
Granted: July 25, 2019
Application Number:
20190229113
Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the…
OPTICAL DRIVER WITH ASYMMETRIC PRE-EMPHASIS
Granted: July 4, 2019
Application Number:
20190207687
An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The…
INLINE ECC FUNCTION FOR SYSTEM-ON-CHIP
Granted: June 27, 2019
Application Number:
20190196901
An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory…
SECURITY FOR PROGRAMMABLE DEVICES IN A DATA CENTER
Granted: June 20, 2019
Application Number:
20190188419
An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region…
PROGRAMMABLE PIPELINE INTERFACE CIRCUIT
Granted: June 13, 2019
Application Number:
20190181863
The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more…
PROGRAMMABLE TEMPERATURE COEFFICIENT ANALOG SECOND-ORDER CURVATURE COMPENSATED VOLTAGE REFERENCE
Granted: June 6, 2019
Application Number:
20190172504
An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the…
PROBE HEAD SECURING MECHANISM FOR PROBE ASSEMBLY
Granted: June 6, 2019
Application Number:
20190170816
Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The…
PUSHER PIN HAVING A NON-ELECTRICALLY CONDUCTIVE PORTION
Granted: May 2, 2019
Application Number:
20190131728
An electrically insulative pusher pin is disclosed. In one example, an electrically insulative pusher pin includes a first plunger member, a second plunger member, and a spring. The first plunger member has a first end and an exposed second end. The second plunger member has a first end and an exposed second end. The second plunger member is movable relative to the first plunger member, where the exposed second ends of the first and second plunger members defining a length of the pusher…
CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME
Granted: May 2, 2019
Application Number:
20190131265
An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second…
UNIVERSAL CONFORMING WORKPRESS MECHANISM FOR SEMICONDUCTOR AND OTHER APPLICATION TESTING
Granted: May 2, 2019
Application Number:
20190128956
An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.
INTERPOSER BLOCK WITH RETRACTABLE SPRING PIN TOP COVER PLATE
Granted: May 2, 2019
Application Number:
20190128955
An interposer block, a chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an interposer block for an integrated circuit chip package test system is provided. The interposer block includes a main body, a retainer plate, and a cover plate. A plurality of spring pins are each disposed in a respective one of a plurality of spring pin receiving holes formed in the main body. The retainer plate is coupled to the main body and…
BALANCED CONFORMING FORCE MECHANISM FOR INTEGRATED CIRCUIT PACKAGE WORKPRESS TESTING SYSTEMS
Granted: May 2, 2019
Application Number:
20190128950
An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is…
DATABASE LOOKUP USING A SCANNABLE CODE FOR PART SELECTION
Granted: April 25, 2019
Application Number:
20190122282
Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum…
QUADRATURE CLOCK CORRECTION CIRCUIT FOR TRANSMITTERS
Granted: April 25, 2019
Application Number:
20190123728
A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal;…
