ADAPTIVE SCHEDULING OF MEMORY REQUESTS
Granted: November 15, 2018
Application Number:
20180329839
Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and…
DYNAMIC SCAN CHAIN RECONFIGURATION IN AN INTEGRATED CIRCUIT
Granted: November 8, 2018
Application Number:
20180321306
An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated…
DYNAMIC MOUNTING THERMAL MANAGEMENT FOR DEVICES ON BOARD
Granted: October 25, 2018
Application Number:
20180308783
Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The…
RECALIBRATION OF SOURCE SYNCHRONOUS SYSTEMS
Granted: October 11, 2018
Application Number:
20180294802
An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first…
ADC BASED RECEIVER
Granted: October 4, 2018
Application Number:
20180287837
A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in…
METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION
Granted: October 4, 2018
Application Number:
20180286826
Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an…
TESTING SYSTEM FOR LID-LESS INTEGRATED CIRCUIT PACKAGES
Granted: October 4, 2018
Application Number:
20180284187
Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a…
DEBUGGING SYSTEM AND METHOD
Granted: September 6, 2018
Application Number:
20180253368
An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller…
MIGRATING ACCELERATORS BETWEEN COMPUTE SYSTEMS
Granted: August 16, 2018
Application Number:
20180232254
Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host,…
CIRCUIT FOR AND METHOD OF IMPLEMENTING A MULTIFUNCTION OUTPUT GENERATOR
Granted: August 9, 2018
Application Number:
20180226929
A circuit for implementing a multifunction output generator is described. The circuit comprises an amplifier circuit having a first input and a second input; a voltage generator coupled at a first node to a first input of the amplifier circuit; a controllable current source configured to provide a variable current to the first node; and a switching circuit enabling the operation of the amplifier circuit in a first mode for sensing a temperature and a second mode for providing a reference…
NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS
Granted: July 19, 2018
Application Number:
20180203956
Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path…
CIRCUITS FOR AND METHODS OF IMPLEMENTING AN INDUCTOR AND A PATTERN GROUND SHIELD IN AN INTEGRATED CIRCUIT
Granted: July 5, 2018
Application Number:
20180190584
An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.
METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED CIRCUIT PACKAGE
Granted: May 24, 2018
Application Number:
20180144963
An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
SEGMENTED ELECTRO-ABSORPTION MODULATION
Granted: May 10, 2018
Application Number:
20180129082
Systems and methods therefor relating generally to electro-absorption modulation are disclosed. In a system thereof, a waveguide is for propagating an optical signal. A segmented electro-absorption modulator (“SEAM”) includes: a segmented anode having at least two anode segments spaced apart from one another alongside a first side of the waveguide; and a segmented cathode having at least two cathode segments spaced apart from one another alongside a second side of the waveguide…
PROGRAMMABLE CLOCK MONITOR
Granted: May 3, 2018
Application Number:
20180121280
An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition,…
DEBUGGING SYSTEM AND METHOD
Granted: April 26, 2018
Application Number:
20180113787
Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on…
IMPEDANCE AND SWING CONTROL FOR VOLTAGE-MODE DRIVER
Granted: April 12, 2018
Application Number:
20180102797
A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the…
SUBSTRATE NOISE ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES
Granted: March 22, 2018
Application Number:
20180083096
An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the…
STACKED COLUMNAR INTEGRATED CIRCUITS
Granted: March 22, 2018
Application Number:
20180083635
An example semiconductor device includes a first integrated circuit (IC) die including a first column of cascade-coupled resource blocks; a second IC die including a second column of cascade-coupled resource blocks, where an active side of the second IC die is mounted to an active side of the first IC die; and a plurality of electrical connections between the active side of the first IC and the active side of the second IC, the plurality of electrical connections including at least one…
METHODS AND CIRCUITS FOR PREVENTING HOLD TIME VIOLATIONS
Granted: March 22, 2018
Application Number:
20180083633
Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is…
