RECEIVER CIRCUIT
Granted: January 3, 2013
Application Number:
20130002410
A receiver circuit includes an analog front-end circuit, a first adaptation circuit, and a second adaptation circuit. A method operates the receiver circuit. The analog front-end circuit is configured to resolve an output signal from an input signal as a function of adjustable parameters. The first adaptation circuit is coupled to the analog front-end circuit and is configured to determine values of the adjustable parameters responsive to the output signal. The second adaptation circuit…
INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS
Granted: December 27, 2012
Application Number:
20120331435
A method of integrated circuit design using through silicon vias (TSVs) can include determining that a stress field to which a first active circuit element of a circuit block is exposed and a stress field to which a second active circuit element of the circuit block is exposed are mismatched. Mismatch between the stress field of the first active circuit element and the stress field of the second active circuit element can be reduced by modifying a layout of the die for a TSV.
STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS
Granted: December 20, 2012
Application Number:
20120319248
A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.
INTERPOSER HAVING AN INDUCTOR
Granted: October 4, 2012
Application Number:
20120248569
An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer.…
SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE
Granted: September 27, 2012
Application Number:
20120241904
An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation…
INTEGRATED CIRCUIT INDUCTOR HAVING A PATTERNED GROUND SHIELD
Granted: September 27, 2012
Application Number:
20120242446
An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include…
CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT
Granted: September 13, 2012
Application Number:
20120229203
A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a…
INTEGRATED CIRCUIT WITH PROGRAMMABLE CIRCUITRY AND AN EMBEDDED PROCESSOR SYSTEM
Granted: August 30, 2012
Application Number:
20120221833
An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further…
MULTIPLE-LOOP SYMMETRICAL INDUCTOR
Granted: August 23, 2012
Application Number:
20120212315
A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops.…
EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE
Granted: August 9, 2012
Application Number:
20120199959
An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the…
T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY
Granted: July 26, 2012
Application Number:
20120188671
An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor;…
EXTENDING A PROCESSOR SYSTEM WITHIN AN INTEGRATED CIRCUIT
Granted: July 19, 2012
Application Number:
20120185674
A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be…
POWER MANAGEMENT WITHIN AN INTEGRATED CIRCUIT
Granted: July 19, 2012
Application Number:
20120185719
An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.
POWER DISTRIBUTION NETWORK
Granted: June 7, 2012
Application Number:
20120139083
In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines.…
DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE
Granted: June 7, 2012
Application Number:
20120139102
In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact…
SEMICONDUCTOR DEVICE WITH STACKED POWER CONVERTER
Granted: June 7, 2012
Application Number:
20120139103
A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside…
CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY
Granted: May 24, 2012
Application Number:
20120131417
Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.
THROUGH SILICON VIA WITH IMPROVED RELIABILITY
Granted: May 17, 2012
Application Number:
20120119374
A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being…
MULTICHIP MODULE FOR COMMUNICATIONS
Granted: May 17, 2012
Application Number:
20120124257
An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks…
LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE
Granted: April 26, 2012
Application Number:
20120098130
A semiconductor device includes a semiconductor die and lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes metal layers and dielectric layers. One of the metal layers includes contact pads corresponding to lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having respective openings for the contact pad. Respective copper posts are disposed on the contact pads. The respective copper post for each contact pad…
