REDUCING STRESS IN MULTI-DIE INTEGRATED CIRCUIT STRUCTURES
Granted: August 8, 2013
Application Number:
20130200511
An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.
RESONATOR CIRCUIT AND METHOD OF GENERATING A RESONATING OUTPUT SIGNAL
Granted: July 18, 2013
Application Number:
20130181783
A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a…
INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY
Granted: July 18, 2013
Application Number:
20130181360
An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure.
DRIVER CIRCUIT AND METHOD OF GENERATING AN OUTPUT SIGNAL
Granted: July 11, 2013
Application Number:
20130176647
A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electro-static discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second…
INTEGRATED CIRCUIT PACKAGE AND METHOD OF ASSEMBLING AN INTEGRATED CIRCUIT PACKAGE
Granted: July 11, 2013
Application Number:
20130175709
A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.
SYSTEMS AND METHODS FOR CHANGING DECODING PARAMETERS IN A COMMUNICATION SYSTEM
Granted: June 20, 2013
Application Number:
20130156118
A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The…
REDUCTION IN DECODER LOOP ITERATIONS
Granted: June 13, 2013
Application Number:
20130151911
An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A…
CONTENTION-FREE MEMORY ARRANGEMENT
Granted: June 13, 2013
Application Number:
20130148450
A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory…
MINIMUM MEAN SQUARE ERROR PROCESSING
Granted: June 6, 2013
Application Number:
20130144926
A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing…
CIRCUIT FOR AND METHOD OF ENABLING THE TRANSFER OF DATA BY AN INTEGRATED CIRCUIT
Granted: May 30, 2013
Application Number:
20130138879
A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer…
MINIMUM MEAN SQUARE ERROR PROCESSING
Granted: May 30, 2013
Application Number:
20130138712
A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing…
EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRATED CIRCUIT
Granted: May 9, 2013
Application Number:
20130117504
An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory…
SYSTEMS AND METHODS FOR DIGITAL PROCESSING BASED ON ACTIVE SIGNAL CHANNELS OF A COMMUNICATION SYSTEM
Granted: April 25, 2013
Application Number:
20130101066
A communication system includes digital signals that carry data and correspond to channels of a composite signal to be transmitted across a communication channel. Active channels are detected and used to configure digital processing. In one embodiment, active channels are detected, where a particular active channel corresponds to the presence of a particular one of the digital signals. Active channel detection may be used to configure pre-distortion of a composite signal to be…
PARALLEL PROCESSING OF NETWORK PACKETS
Granted: April 18, 2013
Application Number:
20130094507
A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the…
MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK
Granted: April 18, 2013
Application Number:
20130093074
An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.
INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH
Granted: March 14, 2013
Application Number:
20130063861
An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the…
DECODER CIRCUIT FOR DOWN-SAMPLING A DIFFERENTIAL MANCHESTER ENCODING
Granted: January 31, 2013
Application Number:
20130027228
Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence…
INTEGRATED CIRCUIT ENABLING THE COMMUNICATION OF DATA AND A METHOD OF COMMUNICATING DATA IN AN INTEGRATED CIRCUIT
Granted: January 24, 2013
Application Number:
20130022136
An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data…
INDUCTIVE STRUCTURE FORMED USING THROUGH SILICON VIAS
Granted: January 24, 2013
Application Number:
20130020675
An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.
METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL
Granted: January 10, 2013
Application Number:
20130009694
An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured…
