CONTROL SET OPTIMIZATION FOR IMPLEMENTING CIRCUIT DESIGNS IN INTEGRATED CIRCUIT DEVICES
Granted: October 3, 2024
Application Number:
20240330558
Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable…
DIRECT MEMORY ACCESS SYSTEM WITH READ REASSEMBLY CIRCUIT
Granted: October 3, 2024
Application Number:
20240330216
A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and…
DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
Granted: October 3, 2024
Application Number:
20240330215
Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the…
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
Granted: October 3, 2024
Application Number:
20240330213
Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.
THERMALLY AWARE STACKING TOPOLOGY
Granted: September 26, 2024
Application Number:
20240321827
A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can…
BACKSIDE POWER
Granted: September 26, 2024
Application Number:
20240321702
A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.
TEMPERATURE SENSORS IN DIE PAIR TOPOLOGY
Granted: September 26, 2024
Application Number:
20240321668
A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit…
FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM
Granted: September 19, 2024
Application Number:
20240314107
Handling port resets in a multi-port system includes monitoring, using a plurality of firewall circuits, a plurality of controllers corresponding to different communication ports for a reset condition. The plurality of controllers are coupled to a direct memory access (DMA) system through a plurality of bridge circuits. A selected firewall circuit detects a reset condition on a selected controller coupled thereto. The selected controller is coupled to a selected bridge circuit of the…
PRE-PLACEMENT CLOCKING IDENTIFICATION AND RESOLUTION FOR CIRCUIT DESIGNS
Granted: September 19, 2024
Application Number:
20240311541
Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to…
ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTS
Granted: August 8, 2024
Application Number:
20240265182
Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the…
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
Granted: August 8, 2024
Application Number:
20240264761
A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a…
RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES
Granted: August 1, 2024
Application Number:
20240256749
Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new…
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION
Granted: July 11, 2024
Application Number:
20240232482
An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using…
SUPPORTING MULTIPLE CONTROLLER CIRCUITS ON A MULTIPLEXED COMMUNICATION BUS
Granted: July 4, 2024
Application Number:
20240220436
A system includes a plurality of controller circuits. The system includes a plurality of target circuits. The system includes a communication bus communicatively linking the plurality of controller circuits with the plurality of target circuits. The communication bus includes a plurality of switches. Each switch of the plurality of switches is connected to a different one of the plurality of controller circuits.
GAIN CALIBRATION WITH QUANTIZER OFFSET SETTINGS
Granted: June 27, 2024
Application Number:
20240213995
Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets,…
BUILD FLOW FOR IMPLEMENTING ARTIFICIAL INTELLIGENCE APPLICATIONS IN PROGRAMMABLE INTEGRATED CIRCUITS
Granted: June 27, 2024
Application Number:
20240211675
A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying…
DYNAMIC PROVISIONING OF PORTIONS OF A DATA PROCESSING ARRAY FOR SPATIAL AND TEMPORAL SHARING
Granted: June 27, 2024
Application Number:
20240211302
Dynamic provisioning of portions of a data processing array includes receiving, from an executing application, a context request. The context request specifies a requested task to be performed by a data processing array. A configuration for the data processing array is selected from a plurality of configurations for the data processing array. The selected configuration conforms with the context request and is capable of performing the requested task. A determination is made whether the…
LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS
Granted: June 27, 2024
Application Number:
20240211138
A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of…
BI-DIRECTIONAL DYNAMIC FUNCTION EXCHANGE
Granted: June 20, 2024
Application Number:
20240202421
Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit…
RUNTIME EFFICIENT MULTI-STAGE ROUTER FLOW FOR CIRCUIT DESIGNS
Granted: June 20, 2024
Application Number:
20240202423
Multi-stage routing for a circuit design includes performing, using computer hardware, a global routing of the circuit design using a hybrid routing graph for a target integrated circuit. The hybrid routing graph includes routing nodes and a plurality of coarsened routing nodes. Each coarsened routing node includes a plurality of constituent routing nodes that are treated as a single node during the global routing. A detailed routing of the circuit design is performed using the computer…
