INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING ARRAY AND MICROCONTROLLER
Granted: February 29, 2024
Application Number:
20240069511
Instruction generation for a data processing array and microcontroller includes generating a tensor-level intermediate representation from a machine learning model using kernel expressions. Statements of the tensor-level intermediate representation are partitioned into a first set of statements and a second set of statements. From the first set of statements, kernel instructions are generated based on a reconfigurable neural engine model. The kernel instructions are executable by a…
SOFTMAX AND LOG SOFTMAX METHOD AND SYSTEM
Granted: February 22, 2024
Application Number:
20240061903
Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases…
LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE
Granted: February 8, 2024
Application Number:
20240046015
Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO…
INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL
Granted: February 8, 2024
Application Number:
20240045692
Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions…
LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE
Granted: February 8, 2024
Application Number:
20240046015
Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO…
INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL
Granted: February 8, 2024
Application Number:
20240045692
Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions…
RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHITECTURE
Granted: January 25, 2024
Application Number:
20240028556
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHITECTURE
Granted: January 25, 2024
Application Number:
20240028556
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
COMPILER-BASED GENERATION OF TRANSACTION ACCURATE MODELS FROM HIGH-LEVEL LANGUAGES
Granted: January 11, 2024
Application Number:
20240012629
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that…
WAVEFORM STIMULUS GENERATION
Granted: January 11, 2024
Application Number:
20240012973
Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according…
COMPILER-BASED GENERATION OF TRANSACTION ACCURATE MODELS FROM HIGH-LEVEL LANGUAGES
Granted: January 11, 2024
Application Number:
20240012629
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that…
WAVEFORM STIMULUS GENERATION
Granted: January 11, 2024
Application Number:
20240012973
Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according…
3D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY
Granted: January 4, 2024
Application Number:
20240005074
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.
CACHED SYSTEM FOR MANAGING STATE VECTORS
Granted: January 4, 2024
Application Number:
20240004794
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.
HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS
Granted: December 14, 2023
Application Number:
20230401480
Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The…
DATAFLOW-BASED COMPUTER PROGRAM VISUALIZATION AND REFACTORING
Granted: December 14, 2023
Application Number:
20230401043
A computer-based visualization and refactoring system is capable of analyzing a computer program to determine computation tasks of the computer program and channels linking the computation tasks. The system generates, in a memory of computer hardware, a dataflow graph having nodes representing the computation tasks and edges representing the channels. The edges connect the nodes. Source code representations of the computation tasks are determined. Execution metrics of the computer…
SPLITTING VECTOR PROCESSING LOOPS WITH AN UNKNOWN TRIP COUNT
Granted: November 30, 2023
Application Number:
20230385040
A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.
CIRCUIT SIMULATION BASED ON AN RTL COMPONENT IN COMBINATION WITH BEHAVIORAL COMPONENTS
Granted: November 23, 2023
Application Number:
20230376662
Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective…
DATA PROCESSING ARRAY INTERFACE HAVING INTERFACE TILES WITH MULTIPLE DIRECT MEMORY ACCESS CIRCUITS
Granted: November 23, 2023
Application Number:
20230376437
An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an…
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
Granted: November 16, 2023
Application Number:
20230370392
An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based…
