FRAMEWORK FOR SYSTEM SIMULATION USING MULTIPLE SIMULATORS
Granted: November 16, 2023
Application Number:
20230367923
A simulation framework is capable modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The…
DEADLOCK DETECTION AND PREVENTION FOR ROUTING PACKET-SWITCHED NETS IN ELECTRONIC SYSTEMS
Granted: November 9, 2023
Application Number:
20230359801
Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH PATH PRIORITIES USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342304
A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342068
A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH CAPTURE USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342030
A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking…
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
Granted: October 19, 2023
Application Number:
20230336179
An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM…
PREDICTING A PERFORMANCE METRIC BASED ON FEATURES OF A CIRCUIT DESIGN AND EXPLAINING MARGINAL CONTRIBUTIONS OF THE FEATURES TO THE PREDICTION
Granted: October 19, 2023
Application Number:
20230334205
A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions…
TIME-DIVISION MULTIPLEXING (TDM) IN INTEGRATED CIRCUITS FOR ROUTABILITY AND RUNTIME ENHANCEMENT
Granted: October 5, 2023
Application Number:
20230318921
Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more…
STATIC AND AUTOMATIC INFERENCE OF INTER-BASIC BLOCK BURST TRANSFERS FOR HIGH-LEVEL SYNTHESIS
Granted: September 28, 2023
Application Number:
20230305949
Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access…
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELERATION
Granted: September 21, 2023
Application Number:
20230297824
A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear…
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELERATION
Granted: September 21, 2023
Application Number:
20230297824
A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear…
ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
Granted: September 14, 2023
Application Number:
20230291405
A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data…
SELECTION OF FULL OR INCREMENTAL IMPLEMENTATION FLOWS IN PROCESSING CIRCUIT DESIGNS
Granted: September 14, 2023
Application Number:
20230289503
A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the…
METHOD AND SYSTEM FOR BUILDING HARDWARE IMAGES FROM HETEROGENEOUS DESIGNS FOR ELETRONIC SYSTEMS
Granted: September 14, 2023
Application Number:
20230289500
Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications…
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
Granted: September 14, 2023
Application Number:
20230289311
An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die…
SPARSE MATRIX DENSE VECTOR MULTLIPLICATION CIRCUITRY
Granted: August 24, 2023
Application Number:
20230267169
Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from…
EXTENSIBLE DEVICE HOSTED ROOT OF TRUST ARCHITECTURE FOR INTEGRATED CIRCUITS
Granted: August 17, 2023
Application Number:
20230259627
An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of…
TESTBENCH FOR SUB-DESIGN VERIFICATION
Granted: August 10, 2023
Application Number:
20230252212
Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list…
MACHINE LEARNING DEPLOYMENT PLATFORM
Granted: August 3, 2023
Application Number:
20230244966
An inference server is capable of receiving a plurality of inference requests from one or more client systems. Each inference request specifies one of a plurality of different endpoints. The inference server can generate a plurality of batches each including one or more of the plurality of inference requests directed to a same endpoint. The inference server also can process the plurality of batches using a plurality of workers executing in an execution layer therein. Each batch is…
NEURAL NETWORK PROCESSING OF REORDERED COLOR FILTER ARRAY FORMATTED IMAGE DATA
Granted: August 3, 2023
Application Number:
20230245269
A rearranger circuit rearranges data elements of each raw image of a plurality of raw images according to a plurality of raw color channel arrays. The data elements of each raw image are input to the rearranger circuit according to instances of a pattern of color channels of a color filter array (CFA). The data elements specify values of the color channels in the instances of the pattern, and each raw color channel array has the data elements of one color channel of the color channels in…
