SCALABLE SCRIBE REGIONS FOR IMPLEMENTING USER CIRCUIT DESIGNS IN AN INTEGRATED CIRCUIT USING DYNAMIC FUNCTION EXCHANGE
Granted: March 30, 2023
Application Number:
20230098098
Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top…
CIRCUIT ARCHITECTURE FOR DETERMINING THRESHOLD RANGES AND VALUES OF A DATASET
Granted: March 30, 2023
Application Number:
20230096400
An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in…
PREDICTION AND OPTIMIZATION OF MULTI-KERNEL CIRCUIT DESIGN PERFORMANCE USING A PROGRAMMABLE OVERLAY
Granted: March 2, 2023
Application Number:
20230065842
Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of…
FLAT SHELL FOR AN ACCELERATOR CARD
Granted: February 23, 2023
Application Number:
20230055704
Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the…
CONTROLLING A DATA PROCESSING ARRAY USING AN ARRAY CONTROLLER
Granted: February 23, 2023
Application Number:
20230057903
An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of…
MULTIPLE OVERLAYS FOR USE WITH A DATA PROCESSING ARRAY
Granted: February 23, 2023
Application Number:
20230053537
Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a…
PLACEMENT OF LOGIC BASED ON RELATIVE ACTIVATION RATES
Granted: February 16, 2023
Application Number:
20230050757
Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects…
PLACEMENT OF LOGIC BASED ON RELATIVE ACTIVATION RATES
Granted: February 16, 2023
Application Number:
20230050757
Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects…
PLACEMENT OF LOGIC BASED ON RELATIVE ACTIVATION RATES
Granted: February 16, 2023
Application Number:
20230050757
Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects…
LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES
Granted: February 9, 2023
Application Number:
20230044581
Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an…
LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES
Granted: February 9, 2023
Application Number:
20230044581
Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an…
DYNAMICALLY ALLOCATED BUFFER POOLING
Granted: February 2, 2023
Application Number:
20230036531
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further…
AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS
Granted: February 2, 2023
Application Number:
20230034736
Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes…
INTER-KERNEL DATAFLOW ANALYSIS AND DEADLOCK DETECTION
Granted: February 2, 2023
Application Number:
20230032302
Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is…
INTER-KERNEL DATAFLOW ANALYSIS AND DEADLOCK DETECTION
Granted: February 2, 2023
Application Number:
20230032302
Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is…
INTER-KERNEL DATAFLOW ANALYSIS AND DEADLOCK DETECTION
Granted: February 2, 2023
Application Number:
20230032302
Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is…
AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS
Granted: February 2, 2023
Application Number:
20230034736
Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes…
DYNAMICALLY ALLOCATED BUFFER POOLING
Granted: February 2, 2023
Application Number:
20230036531
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further…
DYNAMICALLY ALLOCATED BUFFER POOLING
Granted: February 2, 2023
Application Number:
20230036531
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further…
AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS
Granted: February 2, 2023
Application Number:
20230034736
Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes…
