TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM
Granted: July 20, 2023
Application Number:
20230229497
Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device…
HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING
Granted: June 29, 2023
Application Number:
20230205959
An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to…
CIRCULAR BUFFER ARCHITECTURE USING LOCAL MEMORIES WITH LIMITED RESOURCES
Granted: June 29, 2023
Application Number:
20230205452
A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and…
APPLICATION IMPLEMENTATION AND BUFFER ALLOCATION FOR A DATA PROCESSING ENGINE ARRAY
Granted: June 15, 2023
Application Number:
20230185548
Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map…
COMPRESSION OF SPARSE TENSORS
Granted: June 15, 2023
Application Number:
20230185451
Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is…
PIPELINED PROCESSING OF POLYNOMIAL COMPUTATION
Granted: June 8, 2023
Application Number:
20230176819
Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk?1), generates output z-terms 0 through (Nk/2?1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term…
METHOD AND SYSTEM FOR INTERFACING A TESTBENCH TO CIRCUIT SIMULATION
Granted: June 1, 2023
Application Number:
20230169226
Approaches for simulating a circuit include receiving simulation input data from a testbench executing on a computer system by a simulator interface executing on the computer system. The simulator interface receives simulation output data the according to a hardware bus protocol specified by a simulated circuit for communication and simulates handshaking with the simulated circuit according to the hardware bus protocol in response to receiving the simulation input data and simulation…
SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM
Granted: May 18, 2023
Application Number:
20230153156
Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the…
PROTOCOL AWARE BRIDGE CIRCUIT FOR LOW LATENCY COMMUNICATION AMONG INTEGRATED CIRCUITS
Granted: May 18, 2023
Application Number:
20230153260
A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel…
COMPILATION OF NEURAL NETWORKS INTO SUBGRAPHS FOR PROCESSING BY MULTIPLE COMPUTE CIRCUITS
Granted: May 18, 2023
Application Number:
20230153583
Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the…
CIRCUITS AND METHODS FOR MULTIPLYING LARGE INTEGERS OVER A FINITE FIELD
Granted: May 11, 2023
Application Number:
20230142818
Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through Kby determining respective sets of intermediate z-limbs 0 through K- 1 for r-limbs i for i = 0 to K - 1, and summing corresponding ones of the intermediate z-limbs of sets i through K - 1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K - 1 of set 0…
DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE
Granted: May 11, 2023
Application Number:
20230148419
Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s)…
RESOURCE ESTIMATION FOR IMPLEMENTING CIRCUIT DESIGNS WITHIN AN INTEGRATED CIRCUIT
Granted: May 11, 2023
Application Number:
20230144285
Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is…
DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE
Granted: May 11, 2023
Application Number:
20230148419
Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s)…
RESOURCE ESTIMATION FOR IMPLEMENTING CIRCUIT DESIGNS WITHIN AN INTEGRATED CIRCUIT
Granted: May 11, 2023
Application Number:
20230144285
Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is…
CIRCUITS AND METHODS FOR MULTIPLYING LARGE INTEGERS OVER A FINITE FIELD
Granted: May 11, 2023
Application Number:
20230142818
Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through Kby determining respective sets of intermediate z-limbs 0 through K- 1 for r-limbs i for i = 0 to K - 1, and summing corresponding ones of the intermediate z-limbs of sets i through K - 1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K - 1 of set 0…
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
Granted: April 27, 2023
Application Number:
20230131698
A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes…
PRE-CARRY DATA PROCESSING APPARATUS AND METHOD
Granted: April 13, 2023
Application Number:
20230111257
Disclosed approaches for accumulating pre-carry data include initializing hold sum to a sum of a LSB of the first pre-carry word of an input stream and an MSB of a second pre-carry word by a pre-carry processing circuit. For successive pre-carry words, the LSB of pre-carry word i and the MSB of pre-carry word i+1 are summed into a next sum. An FFcount is incremented by an adder circuit if the LSB of the next sum is equal to 0xFF. If the LSB of the next sum is not equal to 0xFF, the…
CIRCUIT DESIGN SIMULATION AND CLOCK EVENT REDUCTION
Granted: April 13, 2023
Application Number:
20230114858
Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The…
DATA TRAFFIC INJECTION FOR SIMULATION OF CIRCUIT DESIGNS
Granted: April 13, 2023
Application Number:
20230113197
Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples…
