Network interface device
Granted: April 23, 2024
Patent Number:
11966351
A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first…
Forming and/or configuring stacked dies
Granted: April 16, 2024
Patent Number:
11961823
Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two…
Network interface device
Granted: April 16, 2024
Patent Number:
11960596
A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust…
Circular buffer architecture using local memories with limited resources
Granted: April 9, 2024
Patent Number:
11954359
A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and…
Parity protection of control registers based on register bit positions
Granted: April 2, 2024
Patent Number:
11947409
An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from…
Integrated circuit package with voltage droop mitigation
Granted: April 2, 2024
Patent Number:
11950358
A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of…
Digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture with tunable impedance control and transition glitch reduction techniques
Granted: April 2, 2024
Patent Number:
11949425
A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the…
Polyphase filter control scheme for fractional resampler systems
Granted: April 2, 2024
Patent Number:
11949395
Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a…
Flexible queue provisioning for partitioned acceleration device
Granted: April 2, 2024
Patent Number:
11947469
Embodiments herein describe partitioning an acceleration device based on the needs of each user application executing in a host. In one embodiment, a flexible queue provisioning method allows the acceleration device to be dynamically partitioned by pushing the configuration through a control command queue to the device by management software running in a trusted zone. The new configuration is parsed and verified by trusted firmware, which, then, creates isolated IO command queues on the…
Multipath memory with static or dynamic mapping to coherent or MMIO space
Granted: April 2, 2024
Patent Number:
11947459
Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.
Systems and methods for digital predistortion to mitigate power amplifier bias circuit effects
Granted: March 26, 2024
Patent Number:
11942904
A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate…
Compression of sparse tensors
Granted: March 26, 2024
Patent Number:
11941248
Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is…
Error aware module redundancy for machine learning
Granted: March 19, 2024
Patent Number:
11934932
Examples herein propose operating redundant ML models which have been trained using a boosting technique that considers hardware faults. The embodiments herein describe performing an evaluation process where the performance of a first ML model is measured in the presence of a hardware fault. The errors introduced by the hardware fault can then be used to train a second ML model. In one embodiment, a second evaluation process is performed where the combined performance of both the first…
Network interface device
Granted: March 5, 2024
Patent Number:
11924032
A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.
DTC nonlinearity correction
Granted: March 5, 2024
Patent Number:
11923857
Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once…
Low-latency time-to-digital converter with reduced quantization step
Granted: March 5, 2024
Patent Number:
11923856
Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay…
Flexible data-driven software control of reconfigurable platforms
Granted: March 5, 2024
Patent Number:
11922223
Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the…
Method for supporting multiple concurrent plugins in a programmable integrated circuit
Granted: February 27, 2024
Patent Number:
11916552
Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking…
Memory self-refresh re-entry state
Granted: February 27, 2024
Patent Number:
11914905
Examples describe memory refresh operations for memory subsystems. One example is a method for a memory controller, the method including entering a first state upon exiting self-refresh state, wherein the first state comprises activating a first timer. The method includes entering a second state from the first state upon detecting an end of an active period and detecting that the first timer has not expired. The method includes entering a third state from the second state upon detecting…
Universal interposer for a semiconductor package
Granted: February 13, 2024
Patent Number:
11901300
A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having…
