Xilinx Patent Grants

Memory utilization in a circuit design

Granted: October 17, 2017
Patent Number: 9792395
The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less…

Mitigation of single event latchup

Granted: October 17, 2017
Patent Number: 9793899
The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in…

M-path filter with outer and inner channelizers for passband bandwidth adjustment

Granted: October 10, 2017
Patent Number: 9787289
Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information…

Precision pulse generation using a serial transceiver

Granted: October 10, 2017
Patent Number: 9787313
An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

Multiplier circuits configurable for real or complex operation

Granted: October 3, 2017
Patent Number: 9778905
A system includes an integrated circuit coupled to the memory. The integrated circuit is configured to receive first and second complex numbers at one or more data inputs. A first value is determined using a first set of product arrays of a first real number multiplier. A second value is determined using a second set of product arrays of the first real number multiplier and a third set of product arrays of a second real number multiplier. A third value is determined using a fourth set of…

Tensor operations and acceleration

Granted: October 3, 2017
Patent Number: 9779786
A system includes global memory circuitry configured to store input tensors and output tensors. Row data paths are each connected to an output port of the memory circuitry. Column data paths are connected to an input port of the memory circuitry. Processing elements are arranged in rows and columns along the row data paths and column data paths, respectively. The processing elements include local memory circuitry configured to store multiple masks and processing circuitry. The processing…

Methods and systems for improving safety of processor system

Granted: September 26, 2017
Patent Number: 9772897
A processing subsystem for providing diagnostic of a processing system is provided. The processing subsystem includes a real-time processing unit that receives a first input that includes data from one or more sensors and processes the first input to generate first output that controls an actuator. The processing subsystem also includes a power and safety management unit that receives a second input and processes the second input to generate second output for testing of the first output.…

Post-placement and pre-routing processing of critical paths in a circuit design

Granted: September 26, 2017
Patent Number: 9773083
Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold…

Effective clamshell mirroring for memory interfaces

Granted: September 26, 2017
Patent Number: 9773543
Methods and apparatus are described for pinning out multiple memory devices using shared conductors therebetween and providing multiple chip select signals to indicate to which of the memory devices address signals on the shared conductors apply. In the case of a clamshell configuration with a top memory device having a corresponding bottom memory device and shared vias coupled therebetween, sharing two address signals for each shared via in this manner reduces the total number of vias…

Method for increasing active inductor operating range and peaking gain

Granted: September 26, 2017
Patent Number: 9774315
Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable…

Reducing artifacts within a video processing system using a buffer management system

Granted: September 26, 2017
Patent Number: 9774866
A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data…

Look-up table restructuring for timing closure in circuit designs

Granted: September 19, 2017
Patent Number: 9767247
A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the…

Interposer-less stack die interconnect

Granted: September 12, 2017
Patent Number: 9761533
Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal…

Linear gain code interleaved automatic gain control circuit

Granted: September 5, 2017
Patent Number: 9755600
An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the…

Protection against tamper using in-rush current

Granted: September 5, 2017
Patent Number: 9755649
A method for protecting an integrated circuit device against security violations includes monitoring a component of the integrated circuit device for security violations. A security violation of the component of the integrated circuit device is then identified. The component of the integrated circuit device is then internally destroyed in response to the identified security violation by providing current to the component beyond a tolerable limit of the component.

Dynamic quantizers having multiple reset levels

Granted: September 5, 2017
Patent Number: 9755655
Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature (“PVT”) and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering…

Generating and checking a quaternary pseudo random binary sequence

Granted: September 5, 2017
Patent Number: 9755792
An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence (“QPRBS”). In an apparatus, there is a pseudo random binary sequence (“PRBS”) generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is…

High throughput packet state processing

Granted: September 5, 2017
Patent Number: 9756154
A system for processing data includes a filtering module having a plurality of processing units, a state accumulator, and a merging network coupled to the processing units and the state accumulator. Each processing unit is configured to output a set of two sub-state vectors and a packet continuance indicator. The state accumulator is configured to store a state resulted from previous processing cycles by the processing units. The merging network is configured to output a master state…

Fast transient low drop-out voltage regulator for a voltage-mode driver

Granted: August 29, 2017
Patent Number: 9746864
An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second…

Phase-locked loop having sampling phase detector

Granted: August 22, 2017
Patent Number: 9742380
An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL…