Registration of a PUF signature and regeneration using a trellis decoder
Granted: September 3, 2024
Patent Number:
12081238
A physically unclonable function includes a circuit that translates a normally distributed sequence of raw sample into a sequence of uniformly distributed binned values across sub-bins of bins. Helper circuitry generates centering values and parity bits based on binned values generated during registration. Each centering value is associated with a raw sample value corresponding to a binned value and indicates an offset of a sub-bin in one of the bins. A distance calculator generates a…
Random reads using multi-port memory and on-chip memory blocks
Granted: September 3, 2024
Patent Number:
12079484
A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.
Reconfigurable neural engine with extensible instruction set architecture
Granted: September 3, 2024
Patent Number:
12079158
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
Opposite-facing interleaved transformer design
Granted: August 27, 2024
Patent Number:
12073973
A transformer includes a first inductor, facing in a first direction and a second inductor, facing in a second direction, the second direction opposite to the first. In one example the first and the second inductors are arranged such that the first inductor's legs extend to an area of the second inductor's head, and the second inductor's legs extend to an area of the first inductor's head.
Method and system for building hardware images from heterogeneous designs for electronic systems
Granted: August 27, 2024
Patent Number:
12073155
Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications…
Circuits and methods for wavelength locking of optical receiver WDM filters
Granted: August 27, 2024
Patent Number:
12072239
An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the…
IC with adaptive chip-to-chip interface to support different chip-to-chip
Granted: August 20, 2024
Patent Number:
12066969
Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C…
Integrated circuit (IC) structure protection scheme
Granted: August 20, 2024
Patent Number:
12068257
Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the…
Learning neural networks of programmable device blocks directly with backpropagation
Granted: August 20, 2024
Patent Number:
12067484
An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.
Multiple overlays for use with a data processing array
Granted: August 20, 2024
Patent Number:
12067406
Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a…
Frequency detector for clock data recovery
Granted: August 13, 2024
Patent Number:
12063129
An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output…
Static block scheduling in massively parallel software defined hardware systems
Granted: August 13, 2024
Patent Number:
12061990
Embodiments herein describe techniques for static scheduling a neural network implemented in a massively parallel hardware system. The neural network may be scheduled using three different scheduling levels referred to herein as an upper level, an intermediate level, and a lower level. In one embodiment, the upper level includes a hardware or software model of the layers in the neural network that establishes a sequential order of functions that operate concurrently in the hardware…
Distributed configuration of programmable devices
Granted: August 6, 2024
Patent Number:
12056505
Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central…
Network attached MPI processing architecture in smartnics
Granted: July 30, 2024
Patent Number:
12050944
Embodiments herein describe a describe an interface shell in a SmartNIC that reduces data-copy overhead in CPU-centric solutions that rely on hardware compute engine (which can include one or more accelerators). The interface shell offloads tag matching and address translation without CPU involvement. Moreover, the interface shell enables the compute engine to read messages directly from the network without extra data copy—i.e., without first copying the data into the CPU's memory.
Micro device with adaptable thermal management device
Granted: July 23, 2024
Patent Number:
12048083
Micro devices having enhanced through heat transfer utilizing plungers extending from a heat spreader are provided. In one example, a micro device is provided that includes a plunger retaining block, a plurality of plungers, a mounting substrate and an integrated circuit (IC) die. The plunger retaining block includes a top surface and a bottom surface. The plurality of plungers extend from the bottom surface of the plunger retaining block with at least some of the plurality of plungers…
Efficiency and quality of service improvements for systems with higher bandwidth clients mixed with lower bandwidth clients
Granted: July 23, 2024
Patent Number:
12047275
Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send…
Memory controller with reduced latency transaction scheduling
Granted: July 23, 2024
Patent Number:
12045502
A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction.…
Single event upset tolerant memory device
Granted: July 23, 2024
Patent Number:
12045469
A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES…
Routing network using global address map with adaptive main memory expansion for a plurality of home agents
Granted: July 23, 2024
Patent Number:
12045187
An integrated circuit (IC) for adaptive memory expansion scheme is proposed, which comprises: a home agent comprising a first memory expansion pool and a second memory expansion pool; a first port connecting the home agent to a first memory expansion device, where the first memory expansion device comprises a first memory pool; a second port connecting the home agent to a second memory expansion device, where the second memory expansion device comprises a second memory pool; a first…
Wideband digital step attenuator and buffer circuitry for a receiver system
Granted: July 16, 2024
Patent Number:
12040766
Attenuation circuitry for a wireless receiver system receives and attenuates an input signal. The attenuation circuitry includes an input pin, coil circuitry, capacitor network circuitry, and inverter circuitry. The input pin receives the input signal. The coil circuitry is electrically connected to the input pin, receives the input signal from the input pin, and outputs an adjusted signal from the input signal. The capacitor network circuitry is electrically connected to the coil…
