ECC optimization
Granted: January 28, 2025
Patent Number:
12212337
An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
Transparent and remote kernel execution in a heterogeneous computing system
Granted: January 21, 2025
Patent Number:
12204940
Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device…
Dynamic data conversion for network computer systems
Granted: January 14, 2025
Patent Number:
12200087
A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and…
Gain calibration with quantizer offset settings
Granted: January 7, 2025
Patent Number:
12191876
Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets,…
Single port memory with multiple memory operations per clock cycle
Granted: January 7, 2025
Patent Number:
12190994
An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and…
Method and apparatus for eliminating inter-link skew in high-speed serial data communications
Granted: January 7, 2025
Patent Number:
12190077
A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the…
Clock recovery circuit
Granted: December 31, 2024
Patent Number:
12183311
A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby…
Splitting vector processing loops with an unknown trip count
Granted: December 31, 2024
Patent Number:
12182552
A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.
Programmable stream switches and functional safety circuits in integrated circuits
Granted: December 24, 2024
Patent Number:
12176896
An integrated circuit (IC) may include a plurality of compute tiles in a data processing array. Each compute tile is configured to perform a data processing function. The IC may include a plurality of interface tiles in the data processing array. The plurality of interface tiles are communicatively linked to the plurality of compute tiles. The IC may include a plurality of programmable stream switches disposed in the plurality of compute tiles and the plurality of interface tiles. The IC…
Buffer circuitry having improved bandwidth and return loss
Granted: December 24, 2024
Patent Number:
12176900
An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the…
Smart cache implementation for image warping
Granted: December 24, 2024
Patent Number:
12175622
A smart cache implementation for image warping is provided by dividing an output image into a plurality of blocks corresponding to initial coordinates in the output image; dividing an input image into at least a first and second regions of pixels, where the first region overlaps the second region; generating an unsorted remap vector of the plurality of blocks for image warping the input image; identifying a first and second subsets of blocks from the plurality of blocks that can be…
Data processing array interface having interface tiles with multiple direct memory access circuits
Granted: December 10, 2024
Patent Number:
12164451
An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an…
DAC-based transmit driver architecture with improved bandwidth
Granted: December 3, 2024
Patent Number:
12160256
A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output…
Shared depthwise convolution
Granted: December 3, 2024
Patent Number:
12159212
A digital processing engine is configured to receive input data from a memory. The input data comprises first input channels. The digital processing engine is further configured to convolve, with a convolution model, the input data. The convolution model comprises a first filter layer configured to generate first intermediate data having first output channels. A number of the first output channels is less than a number of the first input channels. The convolution model further comprises…
Implementing data flows of an application across a memory hierarchy of a data processing array
Granted: December 3, 2024
Patent Number:
12159057
Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object…
Yield recovery scheme for memory
Granted: November 26, 2024
Patent Number:
12154617
A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty…
Method for implementing an I/O buffer
Granted: November 26, 2024
Patent Number:
12153458
An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.
Cascaded reference based thin-oxide only N-well steering circuit for contention solution in multi-supply designs
Granted: November 26, 2024
Patent Number:
12153457
A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering…
Spatial distribution in a 3D data processing unit
Granted: November 19, 2024
Patent Number:
12147369
The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.
Scalable acceleration of reentrant compute operations
Granted: November 19, 2024
Patent Number:
12147379
Examples herein describe techniques for performing parallel processing using a plurality of processing elements (PEs) and a controller for data that has data dependencies. For example, a calculation may require an entire row or column to be summed, or to determine its mean. The PEs can be assigned different chunks of a data set (e.g., a tensor set, a column, or a row) for processing. The PEs can use one or more tokens to inform the controller when they are done with partial processing of…
