Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
Granted: April 4, 2023
Patent Number:
11620490
In the disclosed methods and systems for processing in a neural network system, a host computer system writes a plurality of weight matrices associated with a plurality of layers of a neural network to a memory shared with a neural network accelerator. The host computer system further assembles a plurality of per-layer instructions into an instruction package. Each per-layer instruction specifies processing of a respective layer of the plurality of layers of the neural network, and…
Machine learning based methodology for signal waveform, eye diagram, and bit error rate (BER) bathtub prediction
Granted: April 4, 2023
Patent Number:
11621808
Apparatus and associated methods relate to predicting various transient output waveforms at a receiver's output after an initial neural network model is trained by a receiver's transient input waveform and a corresponding transient output waveform. In an illustrative example, the machine learning model may include an adaptive-ordered auto-regressive moving average external input based on neural networks (NNARMAX) model designed to mimic the performance of a continuous time linear…
Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
Granted: April 4, 2023
Patent Number:
11620490
In the disclosed methods and systems for processing in a neural network system, a host computer system writes a plurality of weight matrices associated with a plurality of layers of a neural network to a memory shared with a neural network accelerator. The host computer system further assembles a plurality of per-layer instructions into an instruction package. Each per-layer instruction specifies processing of a respective layer of the plurality of layers of the neural network, and…
System and method for implementing neural networks in integrated circuits
Granted: March 28, 2023
Patent Number:
11615300
A neural network system includes an input layer, one or more hidden layers, and an output layer. A first layer circuit implements a first layer of the one or more hidden layers. The first layer includes a first weight space including one or more subgroups. A forward path circuit of the first layer circuit includes a multiply and accumulate circuit to receive an input from a layer preceding the first layer; and provide a first subgroup weighted sum using the input and a first plurality…
Packet identification (ID) assignment for routing network
Granted: March 28, 2023
Patent Number:
11615052
Some examples described herein relate to packet identification (ID) assignment for a routing network in a programmable integrated circuit (IC). In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to construct an interference graph based on routes of logical nets through switches in a routing network, and assign identifications to the routes comprising…
Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange
Granted: March 21, 2023
Patent Number:
11610042
Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top…
Systems and methods for systolic array design from a high-level program
Granted: March 14, 2023
Patent Number:
11604758
Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured…
Table based multi-function virtualization
Granted: March 14, 2023
Patent Number:
11606317
Sharing integrated circuit (IC) resources can include receiving, within a communication endpoint of an IC, a plurality of packets from a plurality of different source virtual entities, determining packet handling data for each packet of the plurality of packets using an acceleration function table stored within the IC, routing each packet of the plurality of packets to one or more selected function circuit blocks of a plurality of function circuit blocks in the IC based on the packet…
Beamforming antenna, measurement device, antenna measurement system and method
Granted: March 14, 2023
Patent Number:
11606125
The present invention provides a beamforming antenna (100, 200, 400) comprising a plurality of antenna elements (101, 102, 201, 202, 401, 402, 440), and a signal generator (103, 403) that is configured to generate for each one of the antenna elements (101, 102, 201, 202, 401, 402, 440) a calibration signal (106, 107, 206, 406, 335) for radiation by the respective antenna element (101, 102, 201, 202, 401, 402, 440) and to supply the generated calibration signals (106, 107, 206, 406, 335)…
Radome with integrated passive cooling
Granted: March 14, 2023
Patent Number:
11605886
An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the…
Optimizing hardware design throughput by latency aware balancing of re-convergent paths
Granted: March 14, 2023
Patent Number:
11604751
Embodiments herein describe techniques for preventing a stall when transmitting data between a producer and a consumer in the same integrated circuit (IC). A stall can occur when there is a split point and a convergence point between the producer and consumer. To prevent the stall, the embodiments herein adjust the latencies of one of the paths (or both paths) such that a maximum latency of the shorter path is greater than, or equal to, the minimum latency of the longer path. When this…
Low frequency power supply spur reduction in clock signals
Granted: March 14, 2023
Patent Number:
11604490
Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power…
Device with data processing engine array that enables partial reconfiguration
Granted: March 7, 2023
Patent Number:
11599498
A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying…
Prediction and optimization of multi-kernel circuit design performance using a programmable overlay
Granted: February 28, 2023
Patent Number:
11593547
Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of…
Implementation for a heterogeneous device
Granted: February 28, 2023
Patent Number:
11593126
Implementing a design for a heterogeneous device can include mapping, using computer hardware, a plurality of applications of a design for a device to a plurality of domains of the device, wherein each domain includes a different compute unit, performing, using the computer hardware, validity checking on the plurality of applications, detecting, using the computer hardware, a conflict between two or more of the plurality of applications from the validity checking, and, in response to the…
Runtime measurement of process variations and supply voltage characteristics
Granted: February 21, 2023
Patent Number:
11585854
Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a…
System and method for implementing neural networks in integrated circuits
Granted: February 21, 2023
Patent Number:
11586908
Systems and methods for training a neural network model includes providing a quantization function including a quantization log threshold parameter associated with a log value of a quantization threshold. A quantization training to a neural network model is performed to generate quantized neural network parameters. The quantization training includes: generating first values with a first precision for the neural network parameters; performing a first optimization process to generate an…
Visualization of data buses in circuit designs
Granted: February 21, 2023
Patent Number:
11586791
Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria…
Machine learning model updates to ML accelerators
Granted: February 21, 2023
Patent Number:
11586578
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators…
Hybrid hardware-software coherent framework
Granted: February 21, 2023
Patent Number:
11586369
Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The…
