Low frequency power supply spur reduction in clock signals
Granted: March 14, 2023
Patent Number:
11604490
Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power…
Device with data processing engine array that enables partial reconfiguration
Granted: March 7, 2023
Patent Number:
11599498
A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying…
Prediction and optimization of multi-kernel circuit design performance using a programmable overlay
Granted: February 28, 2023
Patent Number:
11593547
Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of…
Implementation for a heterogeneous device
Granted: February 28, 2023
Patent Number:
11593126
Implementing a design for a heterogeneous device can include mapping, using computer hardware, a plurality of applications of a design for a device to a plurality of domains of the device, wherein each domain includes a different compute unit, performing, using the computer hardware, validity checking on the plurality of applications, detecting, using the computer hardware, a conflict between two or more of the plurality of applications from the validity checking, and, in response to the…
System and method for implementing neural networks in integrated circuits
Granted: February 21, 2023
Patent Number:
11586908
Systems and methods for training a neural network model includes providing a quantization function including a quantization log threshold parameter associated with a log value of a quantization threshold. A quantization training to a neural network model is performed to generate quantized neural network parameters. The quantization training includes: generating first values with a first precision for the neural network parameters; performing a first optimization process to generate an…
Visualization of data buses in circuit designs
Granted: February 21, 2023
Patent Number:
11586791
Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria…
Machine learning model updates to ML accelerators
Granted: February 21, 2023
Patent Number:
11586578
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators…
Hybrid hardware-software coherent framework
Granted: February 21, 2023
Patent Number:
11586369
Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The…
Runtime measurement of process variations and supply voltage characteristics
Granted: February 21, 2023
Patent Number:
11585854
Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a…
Protection against differential power analysis attacks involving initialization vectors
Granted: February 14, 2023
Patent Number:
11582021
Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to…
Power-on reset circuit with reduced detection time
Granted: February 14, 2023
Patent Number:
11581888
A power-on reset circuit with reduced detection time. One example power-on reset circuit generally includes a voltage sensing circuit having an input coupled to a first power supply rail; a variable resistance component having a control input coupled to an output of the voltage sensing circuit and having a first terminal coupled to the first power supply rail; and an amplitude detection circuit having a first input coupled to the first power supply rail and having a second input coupled…
Clock and phase alignment between physical layers and controller
Granted: February 14, 2023
Patent Number:
11581881
An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to…
Method and system for convolution
Granted: February 14, 2023
Patent Number:
11580191
Method and system relating generally to convolution is disclosed. In such a method, an image patch is selected from input data for a first channel of a plurality of input channels of an input layer. The selected image patch is transformed to obtain a transformed image patch. The transformed image patch is stored. Stored is a plurality of predetermined transformed filter kernels. A stored transformed filter kernel of the plurality of stored predetermined transformed filter kernels is…
Subsystem for configuration, security, and management of an adaptive system
Granted: February 14, 2023
Patent Number:
11580057
An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
Distributed watchdog timer and active token exchange
Granted: February 14, 2023
Patent Number:
11579957
A system includes a plurality of watchdog components. Each watchdog component is configured to receive a kick signal from its monitored function to determine whether the monitored function is active. Each watchdog component is further configured to receive a respective token from all watchdog components that the each watchdog component is connected to. The respective token determines whether its respective watchdog component has timed out. Each watchdog component is further configured to…
Reduced power and area efficient receiver circuitry
Granted: February 7, 2023
Patent Number:
11575497
In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first…
Data processing engine arrangement in a device
Granted: February 7, 2023
Patent Number:
11573726
A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at…
Event-based debug, trace, and profile in device with data processing engine array
Granted: January 31, 2023
Patent Number:
11567881
A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the…
Programmable device having hardened circuits for predetermined digital signal processing functionality
Granted: January 31, 2023
Patent Number:
11569820
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as…
Neural network processing system having host controlled kernel acclerators
Granted: January 31, 2023
Patent Number:
11568218
A disclosed neural network processing system includes a host computer system, a RAMs coupled to the host computer system, and neural network accelerators coupled to the RAMs, respectively. The host computer system is configured with software that when executed causes the host computer system to write input data and work requests to the RAMS. Each work request specifies a subset of neural network operations to perform and memory locations in a RAM of the input data and parameters. A graph…
