Event-based debug, trace, and profile in device with data processing engine array
Granted: January 31, 2023
Patent Number:
11567881
A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the…
Scheduling processing of machine learning tasks on heterogeneous compute circuits
Granted: January 24, 2023
Patent Number:
11561826
Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue…
Logical transport overlayed over a physical transport having a tree topology
Granted: January 24, 2023
Patent Number:
11563639
In an example, a system specifies a first configuration of the physical transport network that models a plurality of devices as a corresponding first plurality of nodes having a tree topology. Each node of the first plurality of nodes has at least one first device identifier and at least one first connection identifier to other nodes in the tree topology. The system specifies a second configuration of the logical transport network that models the plurality of devices as the first…
Time constant tracking for digital pre-distortion
Granted: January 24, 2023
Patent Number:
11563453
A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit and adaptation circuitry. The DPD circuit is configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier. The amplifier is configured to output an output signal based on the digital intermediate signal. The DPD circuit includes one or more an infinite impulse response (IIR) filters configured to implement a first transfer function…
Programmable device having hardened circuits for predetermined digital signal processing functionality
Granted: January 24, 2023
Patent Number:
11563435
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as…
Scheduling processing of machine learning tasks on heterogeneous compute circuits
Granted: January 24, 2023
Patent Number:
11561826
Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue…
Applications for hardware accelerators in computing systems
Granted: January 24, 2023
Patent Number:
11561779
An example method of implementing an application for a hardware accelerator having a programmable device coupled to memory is disclosed. The method includes compiling source code of the application to generate logical circuit descriptions of kernel circuits; determining resource availability in a dynamic region of programmable logic of the programmable device, the dynamic region exclusive of a static region of the programmable logic programmed with a host interface configured to…
Logical transport overlayed over a physical transport having a tree topology
Granted: January 24, 2023
Patent Number:
11563639
In an example, a system specifies a first configuration of the physical transport network that models a plurality of devices as a corresponding first plurality of nodes having a tree topology. Each node of the first plurality of nodes has at least one first device identifier and at least one first connection identifier to other nodes in the tree topology. The system specifies a second configuration of the logical transport network that models the plurality of devices as the first…
Time constant tracking for digital pre-distortion
Granted: January 24, 2023
Patent Number:
11563453
A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit and adaptation circuitry. The DPD circuit is configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier. The amplifier is configured to output an output signal based on the digital intermediate signal. The DPD circuit includes one or more an infinite impulse response (IIR) filters configured to implement a first transfer function…
Programmable device having hardened circuits for predetermined digital signal processing functionality
Granted: January 24, 2023
Patent Number:
11563435
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as…
Applications for hardware accelerators in computing systems
Granted: January 24, 2023
Patent Number:
11561779
An example method of implementing an application for a hardware accelerator having a programmable device coupled to memory is disclosed. The method includes compiling source code of the application to generate logical circuit descriptions of kernel circuits; determining resource availability in a dynamic region of programmable logic of the programmable device, the dynamic region exclusive of a static region of the programmable logic programmed with a host interface configured to…
Hardware coherent computational expansion memory
Granted: January 17, 2023
Patent Number:
11556344
Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O device—e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator…
Antenna module and massive MIMO antenna
Granted: January 10, 2023
Patent Number:
11552410
The present invention provides an antenna module for a massive MIMO antenna, the antenna module comprising a plurality of first signal ports, a number of first antenna elements arranged in a first matrix arrangement, wherein a number of rows of the first matrix arrangement and/or a number of columns of the first matrix arrangement equals the number of first signal ports, and a switching matrix that is configured to controllably couple each of the first signal ports either with all first…
Hierarchical access simulation for signaling with more than two state values
Granted: January 3, 2023
Patent Number:
11543452
A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the…
Host-to-kernel streaming support for disparate platforms
Granted: December 27, 2022
Patent Number:
11539770
Providing host-to-kernel streaming support can include determining a platform circuitry for use with a streaming kernel of a circuit design. The streaming kernel is configured for implementation in a user circuitry region of an integrated circuit (IC) to perform tasks offloaded from a host computer. The platform circuitry is configured for implementation in a static circuitry region of the IC. The platform circuitry is configured to establish a communication link with the host computer.…
Network interface device and host processing device
Granted: December 27, 2022
Patent Number:
11537541
A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.
Neural-network pooling
Granted: December 20, 2022
Patent Number:
11531869
Embodiments herein describe circuitry with improved efficiency when executing layers in a nested neural network. As mentioned above, a nested neural network has at least one split operation where a tensor generated by a first layer is transmitted to, and processed by several branches in the neural network. Each of these branches can have several layers that have data dependencies which result in a multiply-add array sitting idly. In one embodiment, the circuitry can include a dedicated…
Application-specific hardware pipeline implemented in an integrated circuit
Granted: December 6, 2022
Patent Number:
11520570
Controlling execution of application-specific hardware pipelines includes detecting, using computer hardware, a loop construct contained in a function within a design specified in a high-level programming language, extracting, using the computer hardware, the loop construct from the function into a newly generated function of the design, and generating, using the computer hardware, a state transition graph corresponding to the loop construct. The state transition graph can be pruned by…
Radome with integrated antenna array and antenna assembly having the same
Granted: December 6, 2022
Patent Number:
11522279
A radome having an integrated antenna array and an antenna assembly having the same are described herein. A method for fabricating a radome having an integrated antenna array is also described herein. In one example, a radome is provided that includes a radome shell and an antenna array. The antenna array has a radiating surface and a backside surface. The radome shell is affixed to the antenna array forming an independent unitary structure separable from other components of an antenna…
Memory tiles in data processing engine array
Granted: December 6, 2022
Patent Number:
11520717
An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory…
