Multi-die integrated circuit with data processing engine array
Granted: March 29, 2022
Patent Number:
11288222
A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die…
Multi-chip structure including a memory die stacked on die having programmable integrated circuit
Granted: March 22, 2022
Patent Number:
11282824
Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first…
High density routing for heterogeneous package integration
Granted: March 22, 2022
Patent Number:
11282776
A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
Chip package assembly with stress decoupled interconnect layer
Granted: March 22, 2022
Patent Number:
11282775
A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a…
Protection of high-level language simulation models
Granted: March 22, 2022
Patent Number:
11281834
Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of…
Memory access protection in programmable logic device
Granted: March 22, 2022
Patent Number:
11281810
Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable…
Control and reconfiguration of data flow graphs on heterogeneous computing platform
Granted: March 22, 2022
Patent Number:
11281440
Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can…
Analog-based DC offset compensation
Granted: March 15, 2022
Patent Number:
11277144
An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the…
Database lookup using a scannable code for part selection
Granted: March 15, 2022
Patent Number:
11276098
Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum…
Compressed tag coherency messaging
Granted: March 8, 2022
Patent Number:
11271860
An example cache-coherent packetized network system includes: a home agent; a snooped agent; and a request agent configured to send, to the home agent, a request message for a first address, the request message having a first transaction identifier of the request agent; where the home agent is configured to send, to the snooped agent, a snoop request message for the first address, the snoop request message having a second transaction identifier of the home agent; and where the snooped…
Loss of signal detection
Granted: March 8, 2022
Patent Number:
11271664
Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a…
Time-multiplexed distribution of analog signals
Granted: March 8, 2022
Patent Number:
11271581
Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does…
Power delivery network for active-on-active stacked integrated circuits
Granted: March 8, 2022
Patent Number:
11270977
An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs…
Model-based design and partitioning for heterogeneous integrated circuits
Granted: March 8, 2022
Patent Number:
11270051
Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data…
RF DAC with low noise spectral density and mismatch spurs
Granted: March 1, 2022
Patent Number:
11265001
A DAC current steering circuit includes first and second transistors, respectively coupled to first and second outputs via first and second nodes at their drains, and source coupled to each other and to ground. A gate of the first transistor is coupled to a data input (D), and a gate of the second transistor coupled to a complement of the data input (DB). The circuit further includes first and second bleeder transistors, whose drains are respectively coupled to the first and second…
Circuit architecture for expanded design for testability functionality
Granted: March 1, 2022
Patent Number:
11263377
A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing…
Configurable network-on-chip for a programmable device
Granted: March 1, 2022
Patent Number:
11263169
An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths…
Virtual hot plug system and method for PCIe devices
Granted: February 22, 2022
Patent Number:
11256648
A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.
Tracing status of a programmable device
Granted: February 22, 2022
Patent Number:
11256520
Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.
Software defined radio (SDR) filter relaxation technique for multiple-input and multiple-output (MIMO) and large antenna array (LAA) applications
Granted: February 15, 2022
Patent Number:
11251822
An example method of operating a radio system includes receiving, over a receiver-path, an RF input signal from an antenna, and converting the RF input signal to fall within a pre-defined frequency range using a local oscillation signal. The method further includes processing the converted input signal with a standard filter. In some examples, the method further includes generating the local oscillation signal in a transmitter path of the radio system.
