Thermal effect mitigation for digital pre-distortion
Granted: February 15, 2022
Patent Number:
11251819
A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier, and an adaptation circuitry configured to update the first parameter based on the adjustment signal, the input signal, and an output signal output by the amplifier and based on the digital intermediate signal. The DPD circuit includes an infinite impulse response filter…
Productivity platform using system-on-chip with programmable circuitry
Granted: February 15, 2022
Patent Number:
11250193
An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay and a processor coupled to the programmable circuitry. The processor can be configured to control the programmable circuitry through execution of a framework. The framework provides high-productivity language control of implementation of the overlay in the programmable circuitry.
Programmed input/output mode
Granted: February 15, 2022
Patent Number:
11249938
A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured…
Governor circuit for system-on-chip
Granted: February 15, 2022
Patent Number:
11249872
An integrated circuit can include a processor configured to execute program code and a plurality of peripheral circuit blocks coupled to the processor. The plurality of peripheral circuit blocks are controlled by the processor as a master. The integrated circuit also can include a governor circuit coupled to the plurality of peripheral circuit blocks. The governor circuit is configured to monitor operation of the plurality of peripheral circuit blocks for known error states and, in…
Micro device with through PCB cooling
Granted: February 8, 2022
Patent Number:
11246211
Micro devices having enhanced through printed circuit board (PCB) heat transfer are provided. In one example, a micro device is provided that includes a PCB, a thermal management device, a chip package, a bracket, and a plurality of extra-package heat conductors. The chip package has a first side facing the thermal management device and a second side mounted to a first side of the PCB. The bracket is disposed on a second side of the PCB that faces away from the chip package. The…
Conversion between raster and coded formats
Granted: February 8, 2022
Patent Number:
11245915
Disclosed approaches for converting between block coded format and raster format include buffers for first type component blocks and second type component blocks of a frame. The buffers are sized less than the width of the frame. A demultiplexer circuit is configured to input the first type component blocks and the second type component blocks in coded block order, and enable storage of the first type component blocks in the first buffer and of the second type component blocks in the…
Network interface device
Granted: February 8, 2022
Patent Number:
11245580
A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.
Frequency detector for clock data recovery
Granted: February 8, 2022
Patent Number:
11245554
An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output…
High-level synthesis vector library for single-instruction multiple data programming and electronic system design
Granted: February 1, 2022
Patent Number:
11238199
A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The…
Multi-chip stacked devices
Granted: February 1, 2022
Patent Number:
11239203
Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective…
Adaptable dynamic region for hardware acceleration
Granted: January 25, 2022
Patent Number:
11232247
Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel…
Protection of electronic designs
Granted: January 25, 2022
Patent Number:
11232219
Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected…
Multi-host direct memory access system for integrated circuits
Granted: January 25, 2022
Patent Number:
11232053
A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the…
Activity-aware clock gating for switches
Granted: January 11, 2022
Patent Number:
11223351
A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports…
Neural network processing system having multiple processors and a neural network accelerator
Granted: January 11, 2022
Patent Number:
11222256
At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data…
Performing multiple functions in single accelerator program without reload overhead in heterogenous computing system
Granted: January 4, 2022
Patent Number:
11216259
Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or…
Pipelined analog-to-digital converter
Granted: January 4, 2022
Patent Number:
11218160
An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and…
Chip package assembly with enhanced interconnects and method for fabricating the same
Granted: January 4, 2022
Patent Number:
11217550
An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled…
Incremental authentication for memory constrained systems
Granted: January 4, 2022
Patent Number:
11216591
Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1?. H1? may be compared with H1 to indicate whether C1 has been…
Converting floating point data into integer data using a dynamically adjusted scale factor
Granted: January 4, 2022
Patent Number:
11216275
The embodiments herein describe a conversion engine that converts floating point data into integer data using a dynamic scaling factor. To select the scaling factor, the conversion engine compares a default (or initial) scaling factor value to an exponent portion of the floating point value to determine a shift value with which to bit shift a mantissa of the floating point value. After bit shifting the mantissa, the conversion engine determines whether the shift value caused an overflow…
