Performing multiple functions in single accelerator program without reload overhead in heterogenous computing system
Granted: January 4, 2022
Patent Number:
11216259
Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or…
Circuit for and method of processing a data stream
Granted: December 28, 2021
Patent Number:
11212072
A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of…
Distribution of inter/intra calibration signals for antenna beamforming signals
Granted: December 28, 2021
Patent Number:
11212016
An example method of calibrating signals in an antenna array includes generating a calibration signal at a first radio sub unit (RSU), transmitting the calibration signal through a transmission path of a radio front end (RFE) of the first RSU, and receiving the calibration signal in a coupling and distribution layer of the first RSU. The method further includes providing the calibration signal from the coupling and distribution layer of the first RSU directly to a coupling and…
Differential analog input buffer
Granted: December 28, 2021
Patent Number:
11211921
A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section…
Integrating amplifier with improved noise rejection
Granted: December 28, 2021
Patent Number:
11211901
An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically…
Reception according to a data transfer protocol of data directed to any of a plurality of destination entities
Granted: December 28, 2021
Patent Number:
11210148
A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a…
Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions
Granted: December 21, 2021
Patent Number:
11204747
Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application…
Efficient determination of parity bit location for polar codes
Granted: December 21, 2021
Patent Number:
11206045
An apparatus for determining a bit index for a parity bit of a polar codeword is disclosed. Each index of a polar codeword may have an associated weight and an associated reliability value. The apparatus may compare the weights and reliability values of a group of bit indices in parallel to determine a bit index of the group associated with the lowest weight and highest reliability value. Additional groups may be processed until all of the bit indices of the polar codeword have been…
Integrated circuit device with stacked dies having mirrored circuitry
Granted: December 21, 2021
Patent Number:
11205639
An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies…
Error re-logging in electronic systems
Granted: December 21, 2021
Patent Number:
11204821
A disclosed circuit arrangement includes a bus interface circuit and a configuration storage circuit coupled to the bus interface circuit. The bus interface circuit stores first error data in the configuration storage circuit in response to detection of an error condition. A second storage circuit provides storage of data, and an error re-logging circuit is coupled to the configuration storage circuit and to the second storage circuit. The error re-logging circuit polls the configuration…
Dataflow graph programming environment for a heterogenous processing system
Granted: December 21, 2021
Patent Number:
11204745
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the…
Unified programmable computational memory and configuration network
Granted: December 14, 2021
Patent Number:
11201623
Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input…
Chip package having a cover with window
Granted: December 14, 2021
Patent Number:
11201095
A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a…
System and method for device synchronization
Granted: December 14, 2021
Patent Number:
11200182
A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the…
Implementing a JTAG device chain in multi-die integrated circuit
Granted: December 14, 2021
Patent Number:
11199582
An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or…
Device monitoring using satellite ADCS having local voltage reference
Granted: December 14, 2021
Patent Number:
11199581
Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be…
Data formatter for convolution
Granted: December 7, 2021
Patent Number:
11194490
A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in…
Slice-aggregated cryptographic system and method
Granted: December 7, 2021
Patent Number:
11196715
A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of…
Technique to improve bandwidth and high frequency return loss for push-pull buffer architecture
Granted: December 7, 2021
Patent Number:
11196412
Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input…
Stacked silicon package assembly having thermal management using phase change material
Granted: December 7, 2021
Patent Number:
11195780
A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.
