Network interface device
Granted: November 2, 2021
Patent Number:
11165720
A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data…
Warpage reduction
Granted: November 2, 2021
Patent Number:
11164749
Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is…
Heterogeneous execution pipeline across different processor architectures and FPGA fabric
Granted: November 2, 2021
Patent Number:
11163605
Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using…
Systems and methods for extending internal endpoints of a network device
Granted: October 26, 2021
Patent Number:
11159445
An integrated circuit (IC) device includes a network device. The network device includes first and second network ports each configured to connect to a network, and an internal endpoint port configured to connect to first endpoint having a first processing unit and second endpoint having a second processing unit. A lookup circuit is configured to provide a first forwarding decision for a first frame to be forwarded to the first endpoint. An endpoint extension circuit is configured to…
Real time memory interface variation tracking
Granted: October 19, 2021
Patent Number:
11152051
A method includes receiving a first and a second data from a first and second IO pad on a first and second data lines respectively. A data strobe is received from a third IO pad on a data strobe line. The first data and the second data are strobed based on the data strobe to generate a first and second strobed data. The first data from the first IO is received at the data strobe line and strobed based on the data strobe to form an another first strobed data and compared to the first…
Metal track routing with buffer bank insertion
Granted: October 19, 2021
Patent Number:
11151298
Examples described herein provide for a technique for metal track routing with buffer bank insertion in a representation of a hardware design of an integrated circuit. In an example, pins of ports of hardblocks in a placed layout are identified. Logical tracks for nets associated with the pins of the ports are generated and assigned to respective metal layers. Logical tracks and corresponding nets are grouped into respective groups. Buffer bank(s) is inserted into the placed layout. Each…
Method and system providing visualization of sub-circuit iterations based on handshake signals
Granted: October 12, 2021
Patent Number:
11144687
Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object…
Data processing system
Granted: October 12, 2021
Patent Number:
11146508
A data processing system has a poll mode driver and a library supporting protocol processing. The poll mode driver and the library are non-operating system functionalities. An application is provided. An operation system is configured while executing in kernel mode and in response to the application being determined to be unresponsive, use a helper process being an operating system functionality executing at user-mode to cause a receive or transmit mode of the application to continue.
Low-noise reference voltage generator
Granted: October 12, 2021
Patent Number:
11146262
A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter…
Stacked silicon package assembly having thermal management
Granted: October 12, 2021
Patent Number:
11145566
A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first…
Secure update of programmable integrated circuits in data center computing environments
Granted: October 12, 2021
Patent Number:
11144652
Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted…
Network interface device supporting multiple interface instances to a common bus
Granted: October 5, 2021
Patent Number:
11138116
A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
Routing in a compilation flow for a heterogeneous multi-core architecture
Granted: October 5, 2021
Patent Number:
11138019
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all…
Systems and methods for efficient parallelized video encoding
Granted: September 28, 2021
Patent Number:
11134256
Methods and systems for parallelized encoding of video are disclosed. According to one embodiment, a video encoder comprises a plurality of encoding engines. Each encoding engine is configured to receive a respective designated region of a video frame and produce respective quantized coefficients, the respective region having one or more unencoded frame blocks. Each encoding engine has a local symcoder for performing entropy-based encoding of the respective quantized coefficients. The…
TCP processing for devices
Granted: September 28, 2021
Patent Number:
11134140
A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.
Dsp cancellation of track-and-hold induced ISI in ADC-based serial links
Granted: September 28, 2021
Patent Number:
11133963
Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a…
Encapsulated accelerator
Granted: September 28, 2021
Patent Number:
11132317
A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the…
Linear interpolator of tabulated functions
Granted: September 28, 2021
Patent Number:
11132296
The embodiments herein store tabulated values representing a linear or non-linear function in separate memory banks to reduce the size of memory used to store the tabulated values while being able to provide upper and lower values for performing linear interpolation in parallel (e.g., the same cycle). To do so, a linear interpolation system includes a first memory bank that stores the even indexed tabulated values while a second memory bank stores the odd indexed tabulated values. During…
Data transfers between a memory and a distributed compute array
Granted: September 21, 2021
Patent Number:
11127442
An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory…
Multi-chip stacked devices
Granted: September 21, 2021
Patent Number:
11127718
Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within…
