Data transfers between a memory and a distributed compute array
Granted: September 21, 2021
Patent Number:
11127442
An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory…
Dual-driver interface
Granted: September 14, 2021
Patent Number:
11119956
A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel…
State machine generation for multi-buffer electronic systems
Granted: September 14, 2021
Patent Number:
11119921
State machine generation for a multi-buffer electronic system can include receiving, using a processor, a user input specifying a reader policy and a number of a plurality of buffers used by a reader and a writer of the multi-buffer electronic system. A state machine can be generated as a data structure. The state machine has a plurality of states determined based on the number of the plurality of buffers and the reader policy. The state machine allocates different buffers of the…
Testing of bonded wafers and structures for testing bonded wafers
Granted: September 14, 2021
Patent Number:
11119146
Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected…
Constraints for applications in a heterogeneous programming environment
Granted: September 7, 2021
Patent Number:
11113030
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a…
Integrated circuit device with electrostatic discharge (ESD) protection
Granted: September 7, 2021
Patent Number:
11114429
Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is…
Multi-die device structures and methods
Granted: September 7, 2021
Patent Number:
11114360
Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the…
IC die with dummy structures
Granted: September 7, 2021
Patent Number:
11114344
Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is…
Dual mode interconnect
Granted: September 7, 2021
Patent Number:
11113223
Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between…
Producer-to-consumer active direct cache transfers
Granted: September 7, 2021
Patent Number:
11113194
The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending…
Virtualized peripheral component interconnect express (PCIe) device
Granted: August 31, 2021
Patent Number:
11106616
Examples described herein generally relate to a Peripheral Connect Interconnect Express (PCIe) device. An example is a non-transitory memory storing a representation of a design that is to be implemented on a programmable integrated circuit. The design includes a classifier module (CM), a message trap engine module (MTEM), and a configuration space. The CM is capable of receiving a PCIe message and is configured to determine whether the PCIe message is a PCIe Type 1 configuration…
Data processing engine (DPE) array routing
Granted: August 31, 2021
Patent Number:
11108644
Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE…
Protocol selection in dependence upon conversion time
Granted: August 31, 2021
Patent Number:
11108633
A data processing system comprising: first and second network ports each operable to support a network connection configured according to one or more of a predetermined set of physical layer protocols; and a processor configured to, on a network message being formed for transmission to a network endpoint accessible over either of the first and second network ports: estimate the total time required to, for each of the predetermined set of physical layer protocols, negotiate a respective…
User-programmable LDPC decoder
Granted: August 31, 2021
Patent Number:
11108410
A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding…
Low noise quadrature signal generation
Granted: August 31, 2021
Patent Number:
11108401
A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality…
System and method for digital pre-distortion circuits
Granted: August 31, 2021
Patent Number:
11108364
A circuit for signal classification in a digital pre-distortion (DPD) system is provided. The circuit includes a first frequency path with a positive frequency translation to generate a first power level corresponding to a signal output of the first frequency path, a second frequency path with a negative frequency translation to generate a second power level corresponding to a signal output of the second frequency path, and a third frequency path configured to filter the input signal via…
Integrated electrical/optical interface with two-tiered packaging
Granted: August 31, 2021
Patent Number:
11107770
An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided…
Implantation for etch stop liner
Granted: August 31, 2021
Patent Number:
11107696
Examples described herein provide for methods for semiconductor processing for forming source/drain regions of transistors. An example is a method for semiconductor processing. An etch stop liner is formed in a semiconductor substrate. Forming the etch stop liner includes implanting etch selectivity dopants into the semiconductor substrate. The etch selectivity dopants form at least part of the etch stop liner. A source/drain cavity is formed in the semiconductor substrate. Forming the…
Circuit arrangements and methods for traversing input feature maps
Granted: August 31, 2021
Patent Number:
11106968
A circuit arrangement includes a buffer, a height traversal circuit configured to generate a sequence of IFM height values in response to first control signals, a width traversal circuit configured to generate a sequence of IFM width values in response to second control signals, a control circuit, and an address generation circuit. The control circuit is configured to input an OFM height, an OFM width, a kernel height, and a kernel width; generate the first control signals at times based…
Serialization in electronic design automation flows
Granted: August 31, 2021
Patent Number:
11106851
Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized…
