Dynamically reconfigurable networking using a programmable integrated circuit
Granted: April 27, 2021
Patent Number:
10990547
A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically…
Configurable overlay on wide memory channels for efficient memory access
Granted: April 27, 2021
Patent Number:
10990517
Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores…
Phase detector offset to resolve CDR false lock
Granted: April 20, 2021
Patent Number:
10985764
An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point,…
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
Granted: April 20, 2021
Patent Number:
10984500
An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; bank…
Compression method for deep neural networks with load balance
Granted: April 20, 2021
Patent Number:
10984308
The present invention relates to artificial neural networks, for example, deep neural networks. In particular, the present invention relates to a compression method considering load balance for deep neural networks and the device thereof. More specifically, the present invention relates to how to compress dense neural networks into sparse neural networks in an efficient way so as to improve utilization of resources of the hardware platform.
Customizable multi queue DMA interface
Granted: April 20, 2021
Patent Number:
10983920
Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic…
Dynamic scan chain and method
Granted: April 13, 2021
Patent Number:
10977404
Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are…
Synchronization headers for serial data transmission with multi-level signaling
Granted: April 13, 2021
Patent Number:
10979210
Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence…
Method and apparatus for multi-voltage domain sequential elements
Granted: April 13, 2021
Patent Number:
10979034
A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data…
Efuse bank and associated anchor bits
Granted: April 13, 2021
Patent Number:
10978167
A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The…
Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip
Granted: April 13, 2021
Patent Number:
10977401
Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification…
Dynamic base address register (BAR) reconfiguration using a peripheral component interconnect express (PCIe) extended configuration space
Granted: April 13, 2021
Patent Number:
10977051
Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by…
Development environment for heterogeneous devices
Granted: April 13, 2021
Patent Number:
10977018
Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator…
Package integration for high bandwidth memory
Granted: April 6, 2021
Patent Number:
10971474
A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
Domain aware data migration in coherent heterogenous systems
Granted: April 6, 2021
Patent Number:
10970217
Embodiments disclosed herein provide a domain aware data migration scheme between processing elements, memory, and various caches in a CC-NUMA system. The scheme creates domain awareness in data migration operations, such as Direct Cache Transfer (DCT) operation, stashing operation, and in the allocation of policies of snoop filters and private, shared, or inline caches. The scheme defines a hardware-software interface to communicate locality information (also referred herein as affinity…
Latency synchronization across clock domains
Granted: April 6, 2021
Patent Number:
10969821
Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second…
Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR)
Granted: April 6, 2021
Patent Number:
10969433
Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses…
Retaining memory during partial reconfiguration
Granted: March 30, 2021
Patent Number:
10963170
Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can…
Flexible address mapping for a NoC in an integrated circuit
Granted: March 30, 2021
Patent Number:
10963421
Embodiments herein describe a SoC that includes a mapper that identifies a destination ID for routing a transaction through a NoC. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC to transmit and receive data using the NoC. In one embodiment, the ingress logic blocks can include the mapper that identifies a destination ID for each transaction. In one embodiment, the mapper can receive a destination ID from the hardware element…
Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
Granted: March 30, 2021
Patent Number:
10963411
Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect…
