Network interface device
Granted: May 18, 2021
Patent Number:
11012411
A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is…
NOC peripheral interconnect interrogation scheme
Granted: May 18, 2021
Patent Number:
11010322
A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the…
Circuits for and methods of calibrating a circuit in an integrated circuit device
Granted: May 11, 2021
Patent Number:
11003203
A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second…
System and method for a forward error correction decoder with error reporting
Granted: May 11, 2021
Patent Number:
11005598
A forward error correction decoder for packing error information of a codeword in the space that was previously occupied by the parity symbols in the decoder output is presented. Specifically, the decoder summarizes error information of the codeword in a summary vector having the size no greater than the total size of the parity symbols. The decoder then outputs the message symbols from the codeword and the summary error vector, which provides the error information of the received…
Temperature-locked loop for optical elements having a temperature-dependent response
Granted: May 11, 2021
Patent Number:
11005572
Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer…
Multi-chip stacked devices
Granted: May 11, 2021
Patent Number:
11004833
Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a…
Multiprocessing flow and massively multi-threaded flow for multi-die devices
Granted: May 11, 2021
Patent Number:
11003827
Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein…
Automated analysis and optimization of circuit designs
Granted: May 11, 2021
Patent Number:
11003826
Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the…
Range computation of bitwise operators
Granted: May 11, 2021
Patent Number:
11003818
A method includes parsing and compiling a software code that includes a constraint bitwise operation with a first operand associated with a first constraint range and a second operand associated with a second constraint range. A first and a second plurality of ranges that spans the first and second constraint range are generated. In some embodiments, each constrained range is converted into a binary format having an upper bit portion and a lower bit portion. The upper bit portion for the…
Relaxation oscillator having a dynamically controllable current source
Granted: May 11, 2021
Patent Number:
11003204
Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter…
Capturing data
Granted: May 4, 2021
Patent Number:
10999303
A data analytical engine receives packets from a number of different network interface devices. The data is a replica of part or all of transmit or receive packets processed in the network interface device. A learning algorithm is applied to data from said different network interface devices and it is determined if an alert is to be generated.
Locked down network interface
Granted: May 4, 2021
Patent Number:
10999246
A logic device and method are provided for intercepting a data flow from a network source to a network destination. A data store holds a set of compliance rules and corresponding actions. A packet inspector is configured to inspect the intercepted data flow and identify from the data store a compliance rule associated with the inspected data flow. A packet filter is configured to, when the data flow is identified as being associated with a compliance rule, carry out an action with…
Programmable termination circuits for programmable devices
Granted: May 4, 2021
Patent Number:
10998904
Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations,…
Non-linearity correction
Granted: May 4, 2021
Patent Number:
10998864
An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first…
CMOS analog circuits having a triode-based active load
Granted: May 4, 2021
Patent Number:
10998307
An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may…
Configurable overlay on wide memory channels for efficient memory access
Granted: April 27, 2021
Patent Number:
10990517
Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores…
Object detection in video
Granted: April 27, 2021
Patent Number:
10990826
Detecting objects in video may include receiving object detections for a plurality of selected frames of a video from a still image detector, wherein the plurality of selected frames are non-adjacent frames of the video, propagating the object detections from the plurality of selected frames to sequential frames of the video adjacent to the plurality of selected frames based on a distance metric and vector flow data for the sequential frames, suppressing false positive object detections…
Programmable pipeline at interface of hardened blocks
Granted: April 27, 2021
Patent Number:
10990555
Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing…
Streaming interconnect architecture for data processing engine array
Granted: April 27, 2021
Patent Number:
10990552
Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination…
Dynamically reconfigurable networking using a programmable integrated circuit
Granted: April 27, 2021
Patent Number:
10990547
A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically…
