Cadence Design Systems Patent Grants

Method and system for debugging a program

Granted: April 25, 2017
Patent Number: 9632912
A system and method of debugging a program may include obtaining a selection of a portion of the program which is between trackable inputs and outputs. The method may also include simulating an execution on the portion of the program, by providing input data via the inputs that was input through said inputs during a recorded execution of the program. The method may further include presenting information relating to the simulated execution on an output device.

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

Granted: April 25, 2017
Patent Number: 9633151
Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components…

Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic design

Granted: April 25, 2017
Patent Number: 9633153
Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies…

Method and system for performing distributed timing signoff and optimization

Granted: April 25, 2017
Patent Number: 9633159
Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

System and method for displaying routing options in an electronic design

Granted: April 25, 2017
Patent Number: 9633163
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.

System and method for performing floating point operations in a processor that includes fixed point operations

Granted: April 11, 2017
Patent Number: 9619205
A computer implemented method for performing floating point operations as part of a processor architecture that also includes fixed point operations is disclosed. The computer implemented method includes providing a group of instructions within the fixed point architecture. A floating point value is split between two programmer visible registers. In a system and method in accordance with the present invention a new form of floating point representation and associated processor…

System, method, and computer program product for electronic design configuration space determination and verification

Granted: April 11, 2017
Patent Number: 9619597
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiments may further include calculating configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of…

Electrical analysis process

Granted: April 11, 2017
Patent Number: 9619604
The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node…

System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects

Granted: April 11, 2017
Patent Number: 9619605
A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit…

Concurrent design process

Granted: April 11, 2017
Patent Number: 9619608
The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include recording, at a client computing device, a plurality of operations associated with an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include generating a script based upon, at least in part, the recorded operations and…

Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Granted: March 28, 2017
Patent Number: 9606179
Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a…

Methods, systems, and articles of manufacture for implementing scalable statistical library characterization for electronic designs

Granted: March 14, 2017
Patent Number: 9594858
Various embodiments scalable statistical library characterization for electronic designs by identifying an electronic design, performing circuit simulations on strongly connected components on a component-by-component basis, performing the logic cone analysis on the entire electronic design, and performing combinations of influences on the electronic design caused by variations of parameters. Some embodiments perform simulations on one or more stronger parameters or the strongest…

Method and system to perform equivalency checks

Granted: March 14, 2017
Patent Number: 9594861
An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.

Systems and methods for viewing analog simulation check violations in an electronic design automation framework

Granted: March 7, 2017
Patent Number: 9589085
A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths…

Method and apparatus for integrating spice-based timing using sign-off path-based analysis

Granted: March 7, 2017
Patent Number: 9589096
Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints…

Methods and devices for a DDR memory driver using a voltage translation capacitor

Granted: March 7, 2017
Patent Number: 9589627
Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of…

Automated processor generation system and method for designing a configurable processor

Granted: February 28, 2017
Patent Number: 9582278
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows…

Method and system for automatically generating executable system-level tests

Granted: February 28, 2017
Patent Number: 9582406
Method and system for automatically generating executable system-level tests. The method includes obtaining a system design including interrelation between components of the system design, actions the components are operable to perform, and constraints relating to the performance of the actions; receiving at least an initial action input to be tested; automatically generating a complete test scenario including: solving a logic layer CSP, including automatically scheduling actions and…

Generation of a random sub-space of the space of assignments for a set of generative attributes for verification coverage closure

Granted: February 28, 2017
Patent Number: 9582458
System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a…

Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms

Granted: February 28, 2017
Patent Number: 9582473
A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a…