Cadence Design Systems Patent Grants

Using smart timing models for gate level timing simulation

Granted: July 18, 2017
Patent Number: 9710579
A system and method for simulating the timing of an integrated circuit design using abstract timing models. An abstract or smart timing model is created as a model of a design component or block having partial timing that includes the timing for the boundary or interface logic but removes timing for internal registers. The smart timing model may additionally preserve the timing for asynchronous or multi-cycle paths, or add interconnect delays for certain internal elements, to ensure…

VIP assisted method and apparatus to enable SOC integration and software development

Granted: July 18, 2017
Patent Number: 9710581
Using verification IP (VIP), the related design IP (DIP) can be integrated into a system on a chip (SOC) without requiring the IP component. Using a normalized framework, a software module can be integrated into the VIP software stack enabling the customized management of the VIP beyond the standard specification defined behaviors. Then, the modified software stack can be used to manage both behaviors defined by the specification and the design specific behaviors. The VIP can then be…

Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs

Granted: July 18, 2017
Patent Number: 9710593
Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a…

System and method for concurrent interconnection diagnostics field

Granted: July 11, 2017
Patent Number: 9702933
Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip…

Reducing mask data volume with elastic compression

Granted: July 11, 2017
Patent Number: 9702934
Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.

Method and apparatus for detecting or correcting multi-bit errors in computer memory systems

Granted: July 11, 2017
Patent Number: 9703625
A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Naturally connecting mixed-signal power networks in mixed-signal simulations

Granted: July 11, 2017
Patent Number: 9703921
A system, method, and computer program product for determining whether a design for a circuit meets design specifications, to facilitate the provision of a manufacturable description of the circuit. A computer-operated circuit simulation tool reads the design for the circuit and a power specification, and selectively internally creates a network connection and inserts a corresponding connect module in the design, for at least one circuit block having an unsupported signal declared in the…

System and method for interchangeable transmission driver output stage and low-power margining mode

Granted: July 11, 2017
Patent Number: 9705499
A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured…

System for concurrent target diagnostics field

Granted: July 4, 2017
Patent Number: 9697324
A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the…

Method and system for automatically generating executable system-level tests

Granted: June 27, 2017
Patent Number: 9690681
A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and…

Method for setting breakpoints in automatically loaded software

Granted: June 27, 2017
Patent Number: 9690686
Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify breakpoint conditions in kernel modules, startup processes, shared libraries, and other automatically loaded software elements before the target environment is initialized. The virtual platform detects specified breakpoints when a file is loaded onto a virtual platform debugger during startup of the environment or initialization of the relevant processes. The virtual platform…

Methods and systems for customizable editing of completed chain of abutted instances

Granted: June 27, 2017
Patent Number: 9690893
Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate…

System and method for identifying an electrical short in an electronic design

Granted: June 20, 2017
Patent Number: 9684748
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one…

Concurrent design process

Granted: June 20, 2017
Patent Number: 9684750
The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without…

Method for representing a photonic waveguide port and port specification

Granted: June 20, 2017
Patent Number: 9684761
Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design…

Methods, systems, and computer program product for implementing three-dimensional operations for electronic designs

Granted: June 6, 2017
Patent Number: 9672308
Disclosed are mechanisms for implementing three-dimensional operations for electronic circuit designs. These mechanisms identify a cross-layer layout portion by identifying a first electronic design as an editable layout portion and a second electronic design as a selectable and non-editable layout portion in a single window, determine a ruler by identifying or generating the ruler for a three-dimensional operation across the first electronic design and the second electronic design on…

Methods, systems, and articles of manufacture for implementing electronic designs with a pseudo-3D analysis mechanism

Granted: June 6, 2017
Patent Number: 9672319
Disclosed are techniques for model-based electronic design implementation with a hybrid solver. These techniques generate an extruded via from a linkage node to a reference metal plane that is added to an analysis model for at least a portion of an electronic design. The analysis model for the at least the portion is generated at least by re-establishing interconnection between the at least the portion and a linkage circuit element with the extruded via. At least the portion of the…

Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designs

Granted: May 30, 2017
Patent Number: 9665682
Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an…

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Granted: May 23, 2017
Patent Number: 9659138
Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal…

Methods, systems, and articles of manufacture for trace warping for electronic designs

Granted: May 23, 2017
Patent Number: 9659142
Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle…