Cadence Design Systems Patent Grants

Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs

Granted: February 7, 2017
Patent Number: 9563737
Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments…

System and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model

Granted: January 31, 2017
Patent Number: 9558307
A system and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model receives chip-design information, including the chip-design model to be tested and one or more attributes for testing the chip design model; receives a first regression simulation test request from the client-side integration client; initiates a proxy instance for a first regression simulation test to be executed by an application programming…

System and method for generating vias in an electronic design by automatically using a hovering cursor indication

Granted: January 10, 2017
Patent Number: 9542084
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design. The method may further include receiving an indication that a cursor is hovering over an overlap associated with the electronic design and in response to receiving the indication, computing one or more via parameters, based upon, at least in part, a topology associated with the overlap. The method…

System and method for automatic correction of flight time skew of timing signals in simulated source synchronous interface operation

Granted: January 10, 2017
Patent Number: 9542512
A system and method are provided for maintaining alignment of timing signals of a source synchronous interface between driver and receiver portions of an electronic system in a behavioral model based simulation environment. The system comprises a memory unit, an analysis controller unit coupled to the memory unit, and a timing alignment unit coupled to the analysis controller unit. The timing alignment unit is executable responsive to the analysis controller unit to generate behavioral…

Methods, systems, and computer-readable media for model order reduction in electromagnetic simulation and modeling

Granted: January 10, 2017
Patent Number: 9542515
Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more…

System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design

Granted: December 27, 2016
Patent Number: 9529962
The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the…

System and method for saddle point locking detection during clock and data recovery

Granted: December 27, 2016
Patent Number: 9531529
The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock…

Method and system for creating improved routing polygon abstracts

Granted: December 20, 2016
Patent Number: 9524364
Methods and systems for creating and implementing improved routing polygon abstracts that can be used to efficiently find areas to route through in electrical designs, where the routing polygon abstracts include at least a horizontal routing polygon abstract, a maximum horizontal routing polygon abstract, a vertical routing polygon abstract, and a maximum vertical routing polygon abstract, that are created through various steps including bloating, shrinking, merging, and extending the…

Efficient monte carlo flow via failure probability modeling

Granted: December 20, 2016
Patent Number: 9524365
A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the…

Annotations to identify objects in design generated by high level synthesis (HLS)

Granted: December 20, 2016
Patent Number: 9524366
Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state…

Optimized fused-multiply-add method and system

Granted: December 13, 2016
Patent Number: 9519458
A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical…

Universal single instruction multiple data multiplier and wide accumulator unit

Granted: December 13, 2016
Patent Number: 9519460
A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable…

Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designs

Granted: December 13, 2016
Patent Number: 9519732
Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analyses on electronic designs. Some embodiments perform squish analysis with a squish pattern library on…

Method for using XOR trees for physically efficient scan compression and decompression logic

Granted: December 6, 2016
Patent Number: 9513335
Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic…

Coverage driven generation of constrained random stimuli

Granted: December 6, 2016
Patent Number: 9514035
A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input device, a generation model and a coverage model from a user. The method may also include using a processor, identifying a coverage item in the coverage model and finding a corresponding element in the generation model corresponding to the coverage item. The method may further include using a processor translating a coverage…

Automatic harmonic number identification for harmonic balance analysis

Granted: November 29, 2016
Patent Number: 9507894
An apparatus and method for identifying an optimal harmonic number of a circuit are disclosed. In a simulation of the circuit, a periodic input waveform up to a particular number of periods is applied to the modeled circuit and an output waveform is obtained in response. In response to detection of a steady state response of the output waveform, embodiments simulate the circuit by applying an additional period of the periodic input waveform and obtaining the output waveform corresponding…

Systems and methods for testing integrated circuit designs

Granted: November 22, 2016
Patent Number: 9501590
A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan…

Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

Granted: November 22, 2016
Patent Number: 9501592
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real…

System and method for assertion publication and re-use

Granted: November 22, 2016
Patent Number: 9501598
A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced…

Implementing synchronous triggers for waveform capture in an FPGA prototyping system

Granted: November 15, 2016
Patent Number: 9495492
An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor…