Cadence Design Systems Patent Grants

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Granted: May 23, 2017
Patent Number: 9659138
Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal…

Methods, systems, and articles of manufacture for trace warping for electronic designs

Granted: May 23, 2017
Patent Number: 9659142
Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle…

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs

Granted: May 16, 2017
Patent Number: 9652579
Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one…

Multi-instantiated block timing optimization

Granted: May 16, 2017
Patent Number: 9652582
Electronic design automation systems and methods are presented for top-down timing budget flow in master-clone scenarios. In some embodiments, different instances of a master-clone block within an integrated circuit design are associated with different constraint files. The different constraint files are based on the different connections of each instance with elements of the integrated circuit design as well as the shared structure of the master-clone block. A top-down timing budget…

System, method, and computer program product for electronic design visualization

Granted: May 9, 2017
Patent Number: 9645715
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the…

Method and system for trace compaction during emulation of a circuit design

Granted: May 9, 2017
Patent Number: 9646120
The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further…

System and method of encoding in a serializer/deserializer

Granted: May 9, 2017
Patent Number: 9647688
A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode…

Method and apparatus for master-clone optimization during circuit analysis

Granted: May 2, 2017
Patent Number: 9639644
A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical…

Apparatus and method for built-in test and repair of 3D-IC memory

Granted: May 2, 2017
Patent Number: 9640279
A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for…

Power domain aware insertion methods and designs for testing and repairing memory

Granted: May 2, 2017
Patent Number: 9640280
Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the…

Method and system for debugging a program

Granted: April 25, 2017
Patent Number: 9632912
A system and method of debugging a program may include obtaining a selection of a portion of the program which is between trackable inputs and outputs. The method may also include simulating an execution on the portion of the program, by providing input data via the inputs that was input through said inputs during a recorded execution of the program. The method may further include presenting information relating to the simulated execution on an output device.

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

Granted: April 25, 2017
Patent Number: 9633151
Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components…

Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic design

Granted: April 25, 2017
Patent Number: 9633153
Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies…

Method and system for performing distributed timing signoff and optimization

Granted: April 25, 2017
Patent Number: 9633159
Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

System and method for displaying routing options in an electronic design

Granted: April 25, 2017
Patent Number: 9633163
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.

System and method for performing floating point operations in a processor that includes fixed point operations

Granted: April 11, 2017
Patent Number: 9619205
A computer implemented method for performing floating point operations as part of a processor architecture that also includes fixed point operations is disclosed. The computer implemented method includes providing a group of instructions within the fixed point architecture. A floating point value is split between two programmer visible registers. In a system and method in accordance with the present invention a new form of floating point representation and associated processor…

System, method, and computer program product for electronic design configuration space determination and verification

Granted: April 11, 2017
Patent Number: 9619597
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiments may further include calculating configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of…

Electrical analysis process

Granted: April 11, 2017
Patent Number: 9619604
The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node…

System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects

Granted: April 11, 2017
Patent Number: 9619605
A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit…

Concurrent design process

Granted: April 11, 2017
Patent Number: 9619608
The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include recording, at a client computing device, a plurality of operations associated with an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include generating a script based upon, at least in part, the recorded operations and…