Cadence Design Systems Patent Grants

Method and system for triple patterning technology (TPT) violation detection and visualization

Granted: August 22, 2017
Patent Number: 9740814
A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a…

Method and apparatus for efficient generation of compact waveform-based timing models

Granted: August 8, 2017
Patent Number: 9727676
For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform…

Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation system

Granted: August 1, 2017
Patent Number: 9721048
In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a…

Concurrent design process

Granted: August 1, 2017
Patent Number: 9721052
The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include displaying, at a first client computing device associated with a first user, at least a portion of an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may further include processing a command at the first client computing device from…

Methods, systems, and articles of manufacture for implementing an electronic design with disconnected field domains

Granted: July 25, 2017
Patent Number: 9715569
Disclosed are techniques for devising an electronic design with disconnected field domains. These techniques identify a plurality of electrically conductive shapes of an electronic design, add a plurality of patches to a model of the electronic design for multiple apertures in the electronic design, analyze the model to generate analysis results for the electronic design, and devise or implement the electronic design based in part or in whole upon the analysis, wherein an aperture of the…

Using smart timing models for gate level timing simulation

Granted: July 18, 2017
Patent Number: 9710579
A system and method for simulating the timing of an integrated circuit design using abstract timing models. An abstract or smart timing model is created as a model of a design component or block having partial timing that includes the timing for the boundary or interface logic but removes timing for internal registers. The smart timing model may additionally preserve the timing for asynchronous or multi-cycle paths, or add interconnect delays for certain internal elements, to ensure…

VIP assisted method and apparatus to enable SOC integration and software development

Granted: July 18, 2017
Patent Number: 9710581
Using verification IP (VIP), the related design IP (DIP) can be integrated into a system on a chip (SOC) without requiring the IP component. Using a normalized framework, a software module can be integrated into the VIP software stack enabling the customized management of the VIP beyond the standard specification defined behaviors. Then, the modified software stack can be used to manage both behaviors defined by the specification and the design specific behaviors. The VIP can then be…

Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs

Granted: July 18, 2017
Patent Number: 9710593
Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a…

System and method for concurrent interconnection diagnostics field

Granted: July 11, 2017
Patent Number: 9702933
Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip…

Reducing mask data volume with elastic compression

Granted: July 11, 2017
Patent Number: 9702934
Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.

Method and apparatus for detecting or correcting multi-bit errors in computer memory systems

Granted: July 11, 2017
Patent Number: 9703625
A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Naturally connecting mixed-signal power networks in mixed-signal simulations

Granted: July 11, 2017
Patent Number: 9703921
A system, method, and computer program product for determining whether a design for a circuit meets design specifications, to facilitate the provision of a manufacturable description of the circuit. A computer-operated circuit simulation tool reads the design for the circuit and a power specification, and selectively internally creates a network connection and inserts a corresponding connect module in the design, for at least one circuit block having an unsupported signal declared in the…

System and method for interchangeable transmission driver output stage and low-power margining mode

Granted: July 11, 2017
Patent Number: 9705499
A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured…

System for concurrent target diagnostics field

Granted: July 4, 2017
Patent Number: 9697324
A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the…

Method and system for automatically generating executable system-level tests

Granted: June 27, 2017
Patent Number: 9690681
A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and…

Method for setting breakpoints in automatically loaded software

Granted: June 27, 2017
Patent Number: 9690686
Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify breakpoint conditions in kernel modules, startup processes, shared libraries, and other automatically loaded software elements before the target environment is initialized. The virtual platform detects specified breakpoints when a file is loaded onto a virtual platform debugger during startup of the environment or initialization of the relevant processes. The virtual platform…

Methods and systems for customizable editing of completed chain of abutted instances

Granted: June 27, 2017
Patent Number: 9690893
Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate…

System and method for identifying an electrical short in an electronic design

Granted: June 20, 2017
Patent Number: 9684748
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one…

Concurrent design process

Granted: June 20, 2017
Patent Number: 9684750
The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without…

Method for representing a photonic waveguide port and port specification

Granted: June 20, 2017
Patent Number: 9684761
Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design…