Cadence Design Systems Patent Grants

Method and system for automatically generating executable system-level tests

Granted: June 27, 2017
Patent Number: 9690681
A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and…

Method for setting breakpoints in automatically loaded software

Granted: June 27, 2017
Patent Number: 9690686
Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify breakpoint conditions in kernel modules, startup processes, shared libraries, and other automatically loaded software elements before the target environment is initialized. The virtual platform detects specified breakpoints when a file is loaded onto a virtual platform debugger during startup of the environment or initialization of the relevant processes. The virtual platform…

Methods and systems for customizable editing of completed chain of abutted instances

Granted: June 27, 2017
Patent Number: 9690893
Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate…

System and method for identifying an electrical short in an electronic design

Granted: June 20, 2017
Patent Number: 9684748
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one…

Concurrent design process

Granted: June 20, 2017
Patent Number: 9684750
The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without…

Method for representing a photonic waveguide port and port specification

Granted: June 20, 2017
Patent Number: 9684761
Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design…

Methods, systems, and computer program product for implementing three-dimensional operations for electronic designs

Granted: June 6, 2017
Patent Number: 9672308
Disclosed are mechanisms for implementing three-dimensional operations for electronic circuit designs. These mechanisms identify a cross-layer layout portion by identifying a first electronic design as an editable layout portion and a second electronic design as a selectable and non-editable layout portion in a single window, determine a ruler by identifying or generating the ruler for a three-dimensional operation across the first electronic design and the second electronic design on…

Methods, systems, and articles of manufacture for implementing electronic designs with a pseudo-3D analysis mechanism

Granted: June 6, 2017
Patent Number: 9672319
Disclosed are techniques for model-based electronic design implementation with a hybrid solver. These techniques generate an extruded via from a linkage node to a reference metal plane that is added to an analysis model for at least a portion of an electronic design. The analysis model for the at least the portion is generated at least by re-establishing interconnection between the at least the portion and a linkage circuit element with the extruded via. At least the portion of the…

Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designs

Granted: May 30, 2017
Patent Number: 9665682
Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an…

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Granted: May 23, 2017
Patent Number: 9659138
Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal…

Methods, systems, and articles of manufacture for trace warping for electronic designs

Granted: May 23, 2017
Patent Number: 9659142
Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle…

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs

Granted: May 16, 2017
Patent Number: 9652579
Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one…

Multi-instantiated block timing optimization

Granted: May 16, 2017
Patent Number: 9652582
Electronic design automation systems and methods are presented for top-down timing budget flow in master-clone scenarios. In some embodiments, different instances of a master-clone block within an integrated circuit design are associated with different constraint files. The different constraint files are based on the different connections of each instance with elements of the integrated circuit design as well as the shared structure of the master-clone block. A top-down timing budget…

System, method, and computer program product for electronic design visualization

Granted: May 9, 2017
Patent Number: 9645715
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the…

Method and system for trace compaction during emulation of a circuit design

Granted: May 9, 2017
Patent Number: 9646120
The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further…

System and method of encoding in a serializer/deserializer

Granted: May 9, 2017
Patent Number: 9647688
A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode…

Method and apparatus for master-clone optimization during circuit analysis

Granted: May 2, 2017
Patent Number: 9639644
A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical…

Apparatus and method for built-in test and repair of 3D-IC memory

Granted: May 2, 2017
Patent Number: 9640279
A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for…

Power domain aware insertion methods and designs for testing and repairing memory

Granted: May 2, 2017
Patent Number: 9640280
Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the…

Method and system for debugging a program

Granted: April 25, 2017
Patent Number: 9632912
A system and method of debugging a program may include obtaining a selection of a portion of the program which is between trackable inputs and outputs. The method may also include simulating an execution on the portion of the program, by providing input data via the inputs that was input through said inputs during a recorded execution of the program. The method may further include presenting information relating to the simulated execution on an output device.