Methods and circuits for reducing clock jitter
Granted: November 28, 2023
Patent Number:
11831323
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.
Low power current mode logic
Granted: November 28, 2023
Patent Number:
11831315
High-speed signal propagation circuits are biased by a temperature-compensating signal-swing calibrator to yield a target output signal amplitude across process, voltage and temperature corners, avoiding the power-consumptive over-biasing conventionally employed to avoid under-amplitude conditions in slow-process, low-voltage and/or high temperature conditions.
High-bandwidth signal driver/receiver
Granted: November 28, 2023
Patent Number:
11831153
A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (?) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series…
Method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth
Granted: November 21, 2023
Patent Number:
11823018
An approach is described for a method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth. According to some embodiments, this approach includes providing a systolic array that includes processing elements which each have some number of storage elements for storing weights. For example, the weights can be reused for different data sets by identifying/capturing a current state of the storage elements,…
Voltage controlled oscillator (VCO) with adaptive temperature compensation
Granted: November 7, 2023
Patent Number:
11811362
Aspects of the present disclosure include systems and methods for temperature adaptive voltage controlled oscillators. In one example, a voltage controlled oscillator includes a cross junction circuit electrically coupled to a temperature dependent input current, and an inductor circuit electrically coupled to the cross junction circuit. The voltage controlled oscillator additionally includes a capacitor bank circuit electrically coupled to the inductor circuit, and an input node that…
Receiver training of reference voltage and equalizer coefficients
Granted: November 7, 2023
Patent Number:
11810633
In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding…
Relative placement by application of layered abstractions
Granted: October 31, 2023
Patent Number:
11803684
Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the…
Phase-locked loop with phase information multiplication
Granted: October 31, 2023
Patent Number:
11804846
A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the…
Method and systems for combining neural networks with genetic optimization in the context of electronic component placement
Granted: October 31, 2023
Patent Number:
11803760
The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based…
Interactive cross-section parameterized cell for wire in circuit design
Granted: October 31, 2023
Patent Number:
11803687
Various embodiments provide for a cross-section parameterized cell, which can enable a user to visualize and interactively define or modify one or more wire instances and related elements/structure of a circuit design from an elevation view (or a side view).
Identifying redundant logic based on clock gate enable condition
Granted: October 24, 2023
Patent Number:
11797747
Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.
System and method for tracing nets across multiple fabrics in an electronic design
Granted: October 17, 2023
Patent Number:
11790149
Embodiments include herein are directed towards a method for electronic circuit design is provided. Embodiments may include allowing, at a graphical user interface, a user to initiate a co-design mode associated with an electronic design. Embodiments may further include allowing, at the GUI, the user to select a shape to trace connectivity from. Embodiments may also include tracing the connectivity of the shape across one or more overlaps and identifying one or more pins associated with…
System and method for routing in an electronic design
Granted: October 17, 2023
Patent Number:
11790147
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may…
Continuous time linear equalizer with active inductor
Granted: October 3, 2023
Patent Number:
11777491
Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.
Methods, systems, and computer program products for efficiently implementing a 3D-IC
Granted: October 3, 2023
Patent Number:
11775723
Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies…
Cell instance charge model for delay calculation
Granted: October 3, 2023
Patent Number:
11775719
Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the…
System, method, and computer program product for augmented reality circuit design
Granted: September 19, 2023
Patent Number:
11763050
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, work instructions corresponding to an electronic circuit. Embodiments may further include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device and displaying at least one instruction at the display screen, wherein displaying includes…
Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference
Granted: June 27, 2023
Patent Number:
11687831
An approach includes receiving a machine learning processing job, executing the machine learning processing job using parallel processing of multiple output pixels each cycle by walking data across processing elements with broadcast weights within regions and executing parallel multiplication operations, and generating an output indicating whether the machine learning processing job was successful or failed. In some embodiments, a schedule of actions is generated for respective machine…
Method, product, and system for automated, guided, and region-based layer density balancing
Granted: June 27, 2023
Patent Number:
11687694
An approach is disclosed herein for balancing layer densities in using an automated process. The approach disclosed herein operates on a region-by-region and layer-by-layer basis to perform parameterized layer balancing. In some embodiments, the process comprises determining densities of respective layers in respective regions, evaluating each layer and region to determine whether operations need to be taken to balance those layers in the corresponding regions, determining what those…
Determining capacitance and resistance-capacitance time constant
Granted: June 13, 2023
Patent Number:
11674989
Various embodiments provide for determining a capacitance (or capacitor value) of a circuit, determining a resistance-capacitance time constant (or RC time constant) of a circuit, or both. The circuit can comprise an integrated circuit (IC), such as a circuit implemented on die. An IC of some embodiments generates a frequency of a dock wave signal (e.g., an output signal) such that the clock wave signal encodes an effective capacitance of the IC, a RC time constant of the IC, or both. A…
