INTEGRATED RING STRUCTURES
Granted: May 2, 2024
Application Number:
20240145383
An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an…
VIRTUAL MACHINE TUNNELING MECHANISM
Granted: May 2, 2024
Application Number:
20240143363
An apparatus comprising a memory device, a system on chip (SoC), including a central processing unit (CPU) to execute a virtual machine to retrieve data from the memory device and transmit the data to a remote input/output (I/O) device coupled to a remote computing platform as memory transaction data; and a port to transmit the memory transaction data as transaction layer packets (TLPs) and a network interface card (NIC) to receive the TLPs, including an interface to receive the TLPs and…
TUNNING CONFIGURATION PARAMETERS FOR GRAPHICS PIPELINE FOR BETTER USER EXPERENCE
Granted: April 25, 2024
Application Number:
20240135485
The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration…
CHANNEL SOUNDING FOR WIRELESS LOCAL AREA NETWORK SENSING
Granted: April 25, 2024
Application Number:
20240137185
This disclosure describes systems, methods, and devices related to WLAN sensing sounding. A device may identify a sensing null data packet (NDP) request frame received from a second device, the sensing NDP request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing NDP request frame; generate an NDP frame using the transmit parameters; and send, in response to the…
MICROELECTRONIC ASSEMBLIES
Granted: April 25, 2024
Application Number:
20240136323
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts…
INTEGRATED INDUCTOR OVER TRANSISTOR LAYER
Granted: April 25, 2024
Application Number:
20240136279
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
Granted: April 25, 2024
Application Number:
20240136277
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate…
IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS
Granted: April 25, 2024
Application Number:
20240136244
Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder…
COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE
Granted: April 25, 2024
Application Number:
20240136243
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.
INITIALIZER FOR CIRCLE DISTRIBUTION FOR IMAGE AND VIDEO COMPRESSION AND POSTURE DETECTION
Granted: April 25, 2024
Application Number:
20240135750
An initializer for circle distribution on a 2D surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. The initializer can also be used for sphere distribution in a 3D shape. The initializer uses a mixed deterministic and iterative/stochastic approach. Using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian…
VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES
Granted: April 25, 2024
Application Number:
20240134527
Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message…
INCREMENTAL NEURAL REPRESENTATION FOR FAST GENERATION OF DYNAMIC FREE-VIEWPOINT VIDEOS
Granted: April 25, 2024
Application Number:
20240135483
Described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. The graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.
DATA PRIVACY PRESERVATION IN MACHINE LEARNING TRAINING
Granted: April 25, 2024
Application Number:
20240135209
A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic…
SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS
Granted: April 25, 2024
Application Number:
20240135076
Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph;…
DATA TRANSFER ENCRYPTION MECHANISM
Granted: April 25, 2024
Application Number:
20240134804
An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.
HARDWARE ASSISTED MEMORY ACCESS TRACKING
Granted: April 25, 2024
Application Number:
20240134803
An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.
NAMED AND CLUSTER BARRIERS
Granted: April 25, 2024
Application Number:
20240134719
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier…
ADJUSTING WORKLOAD EXECUTION BASED ON WORKLOAD SIMILARITY
Granted: April 25, 2024
Application Number:
20240134705
Adjusting workload execution based on workload similarity. A processor may determine a similarity of a first workload to a second workload. The processor may adjust execution of the first workload based on execution parameters of the second workload and the similarity of the first workload to the second workload.
SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY
Granted: April 25, 2024
Application Number:
20240134644
Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand…
CONSTANT MODULO VIA RECIRCULANT REDUCTION
Granted: April 25, 2024
Application Number:
20240134604
Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential…
