SPLIT-GATE STRUCTURE IN TRENCH-BASED SILICON CARBIDE POWER DEVICE
Granted: December 20, 2012
Application Number:
20120319132
An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the…
HIGH VOLTAGE AND HIGH POWER BOOST CONVETER WITH CO-PACKAGED SCHOTTKY DIODE
Granted: December 13, 2012
Application Number:
20120313613
A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad. The bottom cathode is electrically connected to the common die pad. It is emphasized that this abstract is being provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This…
Constant On-Time Switching Regulator Implementing Dual Control Loops
Granted: November 29, 2012
Application Number:
20120299565
A control circuit for a switching regulator implements constant on-time control scheme with synchronous rectification and applies dual control loops to improve light load efficiency and enhance transient response. In one embodiment, the control circuit includes a first control loop configured to control a one-shot timer to generate a control signal to turn on the main switch when the feedback voltage is below a first reference voltage and a minimum off-time duration has expired. The…
Constant On-Time Switching Regulator Implementing Light Load Control
Granted: November 29, 2012
Application Number:
20120299569
A control circuit for a switching regulator implements constant on-time control scheme with synchronous rectification and applies an integrated standard and light load control loop to improve light load efficiency and enhance transient response. In one embodiment, the control circuit includes a reference voltage selection circuit configured to select, based on a low-side current signal, a first reference voltage for standard load condition and a second reference voltage for light load…
FABRICATION OF MOS DEVICE WITH VARYING TRENCH DEPTH
Granted: November 29, 2012
Application Number:
20120302021
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench…
FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE
Granted: November 22, 2012
Application Number:
20120292693
Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench…
VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD
Granted: November 22, 2012
Application Number:
20120293144
A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein…
SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
Granted: November 15, 2012
Application Number:
20120286356
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an…
INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET
Granted: November 8, 2012
Application Number:
20120280307
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in…
Method For Forming Gallium Nitride Semiconductor Device With Improved Forward Conduction
Granted: November 8, 2012
Application Number:
20120282762
A method for forming a gallium nitride based semiconductor diode includes forming Schottky contacts on the upper surface of mesas formed in a semiconductor body formed on a substrate. Ohmic contacts are formed on the lower surface of the semiconductor body. In one embodiment, an insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and ohmic contacts to form the anode and cathode electrodes. In another embodiment, vias…
THROUGH SILICON VIA PROCESSING TECHNIQUES FOR LATERAL DOUBLE-DIFFUSED MOSFETS
Granted: November 1, 2012
Application Number:
20120273878
The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts…
SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION
Granted: August 16, 2012
Application Number:
20120205737
A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT
Granted: July 26, 2012
Application Number:
20120187472
A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the…
Vertical Trench LDMOS Transistor
Granted: July 26, 2012
Application Number:
20120187481
A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric…
CHIP SCALE SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGE AND PROCESS OF MANUFACTURE
Granted: June 28, 2012
Application Number:
20120161307
A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a…
SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE
Granted: June 14, 2012
Application Number:
20120146090
Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator…
OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS
Granted: May 31, 2012
Application Number:
20120132988
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can…
ACCUFET WITH INTEGRATED CLAMPING CIRCUIT
Granted: May 24, 2012
Application Number:
20120126317
The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the…
MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH
Granted: May 24, 2012
Application Number:
20120129328
A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The…
SUBSTRATELESS POWER DEVICE PACKAGES
Granted: May 3, 2012
Application Number:
20120104580
A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
