FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER
Granted: August 8, 2013
Application Number:
20130203225
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region…
FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE
Granted: August 8, 2013
Application Number:
20130203224
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode…
OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS
Granted: May 23, 2013
Application Number:
20130126966
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can…
DUAL CHANNEL TRENCH LDMOS TRANSISTORS AND TRANSISTORS INTEGRATED THEREWITH
Granted: May 16, 2013
Application Number:
20130119465
A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body…
Termination Structure for Gallium Nitride Schottky Diode
Granted: May 16, 2013
Application Number:
20130119394
A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer…
Vertical Gallium Nitride Schottky Diode
Granted: May 16, 2013
Application Number:
20130119393
A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction…
TWO-DIMENSIONAL SHIELDED GATE TRANSISTOR DEVICE AND METHOD OF MANUFACTURE
Granted: May 2, 2013
Application Number:
20130105886
A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The…
Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method
Granted: April 25, 2013
Application Number:
20130099364
A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a…
LED CURRENT CONTROL
Granted: April 25, 2013
Application Number:
20130099684
Parallel light emitting diode channels may be controlled using a pulsed control signal input characterized by an input duty cycle and one or more current sense input signals. Each of the one or more current sense input signals is indicative of a current through a corresponding load channel of one or more load channels. One or more pulsed channel current control signals are provided to one or more corresponding dimming controls correspondingly coupled to the one or more load channels.…
Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers
Granted: March 28, 2013
Application Number:
20130075741
A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP…
Lateral PNP Bipolar Transistor with Narrow Trench Emitter
Granted: March 28, 2013
Application Number:
20130075746
A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation…
Trench MOSFET with Integrated Schottky Barrier Diode
Granted: March 28, 2013
Application Number:
20130075808
A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second…
METHOD OF INTEGRATING HIGH VOLTAGE DEVICES
Granted: March 21, 2013
Application Number:
20130072004
The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of…
METHOD OF INTEGRATING HIGH VOLTAGE DEVICES
Granted: March 21, 2013
Application Number:
20130071994
The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of…
SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES
Granted: March 21, 2013
Application Number:
20130069154
The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are…
Nanotube Semiconductor Devices and Nanotube Termination Structures
Granted: January 17, 2013
Application Number:
20130015494
A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
MOS DEVICE WITH LOW INJECTION DIODE
Granted: January 10, 2013
Application Number:
20130009242
A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region…
LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE
Granted: January 3, 2013
Application Number:
20130001694
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second…
Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages
Granted: December 27, 2012
Application Number:
20120329238
A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a…
POWER MOS DEVICE FABRICATION
Granted: December 27, 2012
Application Number:
20120329225
Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body…
