TRENCH MOSFET DEVICE AND THE PREPARATION METHOD THEREOF
Granted: January 4, 2018
Application Number:
20180005959
A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor…
WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Granted: January 4, 2018
Application Number:
20180005912
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing…
POWER TRENCH MOSFET WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING (UIS) PERFORMANCE AND PREPARATION METHOD THEREOF
Granted: December 28, 2017
Application Number:
20170373139
A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor…
SEMICONDUCTOR POWER DEVICE HAVING SINGLE IN-LINE LEAD MODULE AND METHOD OF MAKING THE SAME
Granted: December 28, 2017
Application Number:
20170372987
A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method…
POWER DEVICE AND PREPARATION METHOD THEREOF
Granted: July 13, 2017
Application Number:
20170200705
A power device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the…
POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD
Granted: June 29, 2017
Application Number:
20170186675
A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor…
TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED BREAKDOWN VOLTAGE
Granted: June 22, 2017
Application Number:
20170179107
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top…
TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE
Granted: May 25, 2017
Application Number:
20170148910
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…
BATTERY PROTECTION PACKAGE AND PROCESS OF MAKING THE SAME
Granted: April 6, 2017
Application Number:
20170098626
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and…
SYSTEM AND METHOD FOR EXTENDING THE MAXIMUM DUTY CYCLE OF A STEP-DOWN SWITCHING CONVERTER WITHOUT MAXIMUM DUTY CONTROL
Granted: March 30, 2017
Application Number:
20170093281
The invention proposes a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More particularly, the LEB signal is connected to a slope generator and/or a current sense network. In each switching cycle, the LEB signal…
ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS
Granted: March 9, 2017
Application Number:
20170069750
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
VOLTAGE DETECTION CIRCUIT AND A METHOD OF DETECTING VOLTAGE CHANGES
Granted: March 2, 2017
Application Number:
20170059630
A power conversion system and a method for voltage change detection, specifically, relates to a detection circuit implemented in the AC-DC power converter, detect the voltage change. The AC input voltage is rectified to convert into a DC input voltage transmitted to a detection unit generating a detection voltage signal at different logical states corresponding to the input voltage changes. A charge current source unit is used for charging the capacitor when the detection voltage signal…
FLYBACK CONVERTER OUTPUT CURRENT EVALUATION CIRCUIT AND EVALUATION METHOD
Granted: February 16, 2017
Application Number:
20170047853
An output current calculating circuit for a flyback converter operating under CCM and DCM is disclosed. The off current value IOFF and the blanking current value ILEB flowing through a sensing resistor are calculated using a detection module and are summed together using a current summing unit. A voltage converted from the sum value of the off current value IOFF and the blanking current value ILEB is transmitted through an output stage in a predetermined time ratio of a cycle with the…
BATTERY PROTECTION PACKAGE AND PROCESS OF MAKING THE SAME
Granted: February 2, 2017
Application Number:
20170033060
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and…
METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
Granted: January 26, 2017
Application Number:
20170025356
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD
Granted: December 29, 2016
Application Number:
20160379918
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…
POWER SEMICONDUCTOR PACKAGE DEVICE HAVING LOCKING MECHANISM, AND PREPARATION METHOD THEREOF
Granted: December 29, 2016
Application Number:
20160379917
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first…
NOVEL PULSE TRANSFORMER
Granted: December 8, 2016
Application Number:
20160358705
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
POWER SUPPLY DEVICE
Granted: December 8, 2016
Application Number:
20160359421
The present invention relates to a power supply device for voltage converter, which includes a master switch, a first controller for generating a first pulse signal to drive the master switch to be turned on and turned off, a second controller for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage to determine the logic state of a control signal generated by the second controller, and a coupling element connected between the…
VOLTAGE CONVERTER
Granted: December 8, 2016
Application Number:
20160359419
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
